Patents by Inventor Hsi Wu

Hsi Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11587845
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a die stack disposed over the substrate, a heat spreader disposed over the substrate and having a surface facing the substrate, and a thermal interface material (TIM) disposed between the die stack and the heat spreader. A bottommost die of the die stack includes a surface exposed from remaining dies of the die stack from a top view perspective; and the TIM is in contact with the exposed surface of the bottommost die and the surface of the heat spreader, and is in contact with a sidewall of at least one of the plurality of dies of the die stack.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: February 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chi-Hsi Wu, Wensen Hung, Tsung-Shu Lin, Shih-Chang Ku, Tsung-Yu Chen, Hung-Chi Li
  • Patent number: 11566091
    Abstract: The present invention relates to an ethylene-vinyl alcohol copolymer (EVOH) resin composition, an EVOH film formed therefrom, and a multilayer structure containing the same. The core height difference (Sk) of the surface of the EVOH resin composition is between 0.6 and 2.0 ?m, and the overall standard deviation of Sk is between 0.05 and 0.55. The invention can reduce the torque output during processing to achieve the effect of energy saving, and can also improve the stability during output to obtain a better film appearance.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: January 31, 2023
    Assignee: CHANG CHUN PETROCHEMICAL CO., LTD.
    Inventors: Yu Hsiu Li, Hou Hsi Wu, Wen Hsin Lin
  • Publication number: 20230014813
    Abstract: A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.
    Type: Application
    Filed: September 26, 2022
    Publication date: January 19, 2023
    Inventors: Chen-Hua Yu, Hsing-Kuo Hsia, Sung-Hui Huang, Kuan-Yu Huang, Kuo-Chiang Ting, Shang-Yun Hou, Chi-Hsi Wu
  • Patent number: 11546451
    Abstract: An electronic device is provided the disclosure. The electronic device includes: a body; an image capture device, rotatably disposed on the body to capture an image of an object; a display, configured at a first side of the body and including a display zone, the display zone is configured to display the image of the object; a motor set, electronically connected with the image capture device; and a processor, electronically connected with the image capture device, the display, and the motor set and configured to control the motor set, wherein the display zone includes a center part, when at least part of the object displayed at the display zone is not in the center part, the processor controls the motor set to drive the image capture device to track the object.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: January 3, 2023
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: I-Hsi Wu, Jen-Pang Hsu, Ching-Hsuan Chen
  • Publication number: 20220403078
    Abstract: The present invention relates to an ethylene-vinyl alcohol copolymer (EVOH) resin composition, an EVOH film formed therefrom, and a multilayer structure containing the same. The core height difference (Sk) of the surface of the EVOH resin composition is between 0.6 and 2.0 ?m, and the overall standard deviation of Sk is between 0.05 and 0.55. The invention can reduce the torque output during processing to achieve the effect of energy saving, and can also improve the stability during output to obtain a better film appearance.
    Type: Application
    Filed: March 22, 2022
    Publication date: December 22, 2022
    Inventors: Yu Hsiu LI, Hou Hsi WU, Wen Hsin LIN
  • Patent number: 11532585
    Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chiang Ting, Chi-Hsi Wu, Shang-Yun Hou, Tu-Hao Yu, Chia-Hao Hsu, Ting-Yu Yeh
  • Publication number: 20220399301
    Abstract: A semiconductor package structure includes a conductive structure, at least one semiconductor element, an encapsulant, a redistribution structure and a plurality of bonding wires. The semiconductor element is disposed on and electrically connected to the conductive structure. The encapsulant is disposed on the conductive structure to cover the semiconductor element. The redistribution structure is disposed on the encapsulant, and includes a redistribution layer. The bonding wires electrically connect the redistribution structure and the conductive structure.
    Type: Application
    Filed: August 22, 2022
    Publication date: December 15, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Wei CHANG, Shang-Wei YEH, Chung-Hsi WU, Min Lung HUANG
  • Patent number: 11527454
    Abstract: An embodiment is a method including: attaching a first die to a first side of a first component using first electrical connectors, attaching a first side of a second die to first side of the first component using second electrical connectors, attaching a dummy die to the first side of the first component in a scribe line region of the first component, adhering a cover structure to a second side of the second die, and singulating the first component and the dummy die to form a package structure.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: December 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Hsin Wei, Chi-Hsi Wu, Shang-Yun Hou, Jing-Cheng Lin, Hsien-Pin Hu, Ying-Ching Shih, Szu-Wei Lu
  • Publication number: 20220391061
    Abstract: A portable electronic device and a one-hand touch operation method thereof are provided. A touch operation performed on a touch screen is detected. When a shift amount of the touch operation in a first direction is greater than a first threshold, whether to activate a one-hand mode is determined according to a shift amount of the touch operation in a second direction. When the one-hand mode is activated, the operation interface image is zoomed out or shifted, and displayed in a one-hand mode interface display region.
    Type: Application
    Filed: May 24, 2022
    Publication date: December 8, 2022
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Meng Chen Hsieh, CHEN-YU HSU, Chih-Hsien Yang, I-Hsi Wu, HSIN-YI PU
  • Patent number: 11512196
    Abstract: The instant disclosure relates to a fluorine-containing ethylene-vinyl alcohol copolymer (EVOH) resin composition as well as mixture and blend thereof. The fluorine-containing EVOH resin composition comprises EVOH and fluorine-containing particles, wherein the fluorine-containing EVOH resin composition has a total fluoride ion content ranging from 45 to 41000 ppm. The invention can reduce the adhesion of EVOH to the inside of the extruder, and effectively reduce the appearance of gel or gelled substance in subsequent finished products.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: November 29, 2022
    Assignee: CHANG CHUN PETROCHEMICAL CO., LTD.
    Inventors: Hou Hsi Wu, Yu Hsiu Li, Wen Hsin Lin
  • Patent number: 11510467
    Abstract: A luggage includes a luggage main body, a partition board stitched with its bottom side to the bottom side of the luggage main body, an inner zip fastener provided between the partition board and the luggage main body so that the partition board can open or close a first storage chamber in the luggage main body, a luggage cover stitched with its bottom side to the bottom side of the luggage main body, and an outer zip fastener provided between the luggage cover and the luggage main body so that the luggage cover can open or close a second storage chamber that is defined between the luggage cover and the luggage main body.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: November 29, 2022
    Assignee: C & C LUGGAGE MANUFACTURING CO., LTD.
    Inventor: Hsi-Wu Chiang
  • Patent number: 11508696
    Abstract: A semiconductor device includes a first electronic component, a second electronic component, a third electronic component, a plurality of first interconnection structures, and a plurality of second interconnection structures. The second electronic component is between the first electronic component and the third electronic component. The first interconnection structures are between and electrically connected to the first electronic component and the second electronic component. Each of the first interconnection structures has a length along a first direction substantially parallel to a surface of the first electronic component and a width along a second direction substantially parallel to the surface and substantially perpendicular to the first direction. The length is larger than the width. The second interconnection structures are between and electrically connected to the second electronic component and the third electronic component.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Weiming Chris Chen, Tu-Hao Yu, Kuo-Chiang Ting, Shang-Yun Hou, Chi-Hsi Wu
  • Patent number: 11508695
    Abstract: An embodiment package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and a conductive line electrically connecting a first conductive via to a second conductive via. The conductive line includes a first segment over the first integrated circuit die and having a first lengthwise dimension extending in a first direction and a second segment having a second lengthwise dimension extending in a second direction different than the first direction. The second segment extends over a boundary between the first integrated circuit die and the encapsulant.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Publication number: 20220365278
    Abstract: A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Inventors: Chen-Hua Yu, Hsing-Kuo Hsia, Kuo-Chiang Ting, Sung-Hui Huang, Shang-Yun Hou, Chi-Hsi Wu
  • Publication number: 20220367335
    Abstract: A semiconductor device includes a dielectric interposer, a first redistribution layer, a second redistribution layer and conductive structures. The conductive structures are through the dielectric interposer, wherein the conductive structures are electrically connected to the first redistribution layer and the second redistribution layer. Each of the conductive structures has a tapered profile. A width of each of the conductive structures proximal to the first redistribution layer is narrower than a width of each of the conductive structure proximal to the second redistribution layer.
    Type: Application
    Filed: July 29, 2022
    Publication date: November 17, 2022
    Inventors: KUO-CHIANG TING, CHI-HSI WU, SHANG-YUN HOU, TU-HAO YU, CHIA-HAO HSU, PIN-TSO LIN, CHIA-HSIN CHEN
  • Publication number: 20220359284
    Abstract: Embodiments provide a high aspect ratio via for coupling a top electrode of a vertically oriented component to the substrate, where the top electrode of the component is coupled to the via by a conductive bridge, and where the bottom electrode of the component is coupled to substrate. Some embodiments provide for mounting the component by a component wafer and separating the components while mounted to the substrate. Some embodiments provide for mounting individual components to the substrate.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 10, 2022
    Inventors: Chen-Hua Yu, Chi-Hsi Wu, Wen-Chih Chiou, Tsang-Jiuh Wu, Der-Chyang Yeh, Ming Shih Yeh, An-Jhih Su
  • Publication number: 20220359377
    Abstract: A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 10, 2022
    Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Wen-Chih Chiou, Tsang-Jiuh Wu, Der-Chyang Yeh, Ming Shih Yeh
  • Publication number: 20220359470
    Abstract: A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 10, 2022
    Inventors: Chen-Hua Yu, An-Jhih Su, Wei-Yu Chen, Ying-Ju Chen, Tsung-Shu Lin, Chin-Chuan Chang, Hsien-Wei Chen, Wei-Cheng Wu, Li-Hsien Huang, Chi-Hsi Wu, Der-Chyang Yeh
  • Publication number: 20220361332
    Abstract: A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 10, 2022
    Inventors: Cheng-Hsien Hsieh, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Hsien-Wei Chen, Li-Han Hsu, Wei-Cheng Wu
  • Publication number: 20220359355
    Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 10, 2022
    Inventors: Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang, Chih-Ta Shen, Szu-Wei Lu, Ying-Ching Shih, Wen-Chih Chiou, Chi-Hsi Wu, Chen-Hua Yu