Patents by Inventor Hsi Wu
Hsi Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240009849Abstract: A hand-eye calibration method and a hand-eye calibration device for a robot arm are provided. The method includes following steps. A first mapping relationship between a base of the robot arm and a terminal of the robot arm and a second mapping relationship between a camera and a target object are obtained. Based on a scale, a third mapping relationship between the terminal of the robot arm and a tool set mounted on the terminal and a fourth mapping relationship between the camera and the base in each dimension are updated to minimize an error between a position of the target object in an image captured by the camera and a position of the tool set. In response to the error being convergent and the scale being less than or equal to a scale threshold, the third mapping relationship and the fourth mapping relationship calibrated by the scale are output.Type: ApplicationFiled: May 10, 2023Publication date: January 11, 2024Applicant: PEGATRON CORPORATIONInventors: Ke-Jung Huang, Chao-Chien Lee, Jen-Hui Wang, Chun-Hsi Wu
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Patent number: 11852868Abstract: A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.Type: GrantFiled: July 26, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Hua Yu, Hsing-Kuo Hsia, Kuo-Chiang Ting, Sung-Hui Huang, Shang-Yun Hou, Chi-Hsi Wu
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Patent number: 11842983Abstract: The semiconductor structure includes a plurality of first dies, a plurality of second dies disposed over each of the first dies, and a dielectric material surrounding the plurality of first dies and the plurality of second die. Each of the second dies overlaps a portion of each first die.Type: GrantFiled: November 12, 2021Date of Patent: December 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chen-Hua Yu, Chi-Hsi Wu, Der-Chyang Yeh, Hsien-Wei Chen, An-Jhih Su, Tien-Chung Yang
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Patent number: 11837587Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.Type: GrantFiled: January 3, 2022Date of Patent: December 5, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yu Chen, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Li-Hsien Huang, Po-Hao Tsai, Ming-Shih Yeh, Ta-Wei Liu
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Publication number: 20230350142Abstract: A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.Type: ApplicationFiled: July 5, 2023Publication date: November 2, 2023Inventors: Chen-Hua Yu, Hsing-Kuo Hsia, Sung-Hui Huang, Kuan-Yu Huang, Kuo-Chiang Ting, Shang-Yun Hou, Chi-Hsi Wu
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Patent number: 11764139Abstract: A semiconductor device includes a substrate, a first redistribution layer (RDL) over a first side of the substrate, one or more semiconductor dies over and electrically coupled to the first RDL, and an encapsulant over the first RDL and around the one or more semiconductor dies. The semiconductor device also includes connectors attached to a second side of the substrate opposing the first side, the connectors being electrically coupled to the first RDL. The semiconductor device further includes a polymer layer on the second side of the substrate, the connectors protruding from the polymer layer above a first surface of the polymer layer distal the substrate. A first portion of the polymer layer contacting the connectors has a first thickness, and a second portion of the polymer layer between adjacent connectors has a second thickness smaller than the first thickness.Type: GrantFiled: July 12, 2021Date of Patent: September 19, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jing-Cheng Lin, Chi-Hsi Wu, Chen-Hua Yu, Po-Hao Tsai
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Patent number: 11728254Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.Type: GrantFiled: May 22, 2020Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang, Chih-Ta Shen, Szu-Wei Lu, Ying-Ching Shih, Wen-Chih Chiou, Chi-Hsi Wu, Chen-Hua Yu
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Patent number: 11721559Abstract: A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.Type: GrantFiled: May 23, 2022Date of Patent: August 8, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua Yu, Hsien-Wei Chen, Chi-Hsi Wu, Der-Chyang Yeh, An-Jhih Su, Wei-Yu Chen
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Publication number: 20230245903Abstract: A semiconductor device includes a first die extending through a molding compound layer, a first dummy die having a bottom embedded in the molding compound layer, wherein a height of the first die is greater than a height of the first dummy die, and an interconnect structure over the molding compound layer, wherein a first metal feature of the interconnect structure is electrically connected to the first die and a second metal feature of the interconnect structure is over the first dummy die and extends over a sidewall of the first dummy die.Type: ApplicationFiled: April 10, 2023Publication date: August 3, 2023Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Hsien-Wei Chen, Wei-Yu Chen
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Patent number: 11709574Abstract: An electronic device includes a display and a processor. The processor is electrically coupled to the display. The processor is configured to execute a plurality of program instructions to perform the following steps: defining a window display region and an interface display region on the display when the electronic device is operated in a one-hand operation mode; displaying a desktop display interface corresponding to the one-hand operation mode in the interface display region; and displaying a plugin in the window display region.Type: GrantFiled: March 8, 2022Date of Patent: July 25, 2023Assignee: ASUSTEK COMPUTER INC.Inventors: Yun-Ju Chen, Yu-Chi Huang, Chen-Yu Hsu, Chih-Hsien Yang, I-Hsi Wu, Hsin-Yi Pu
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Publication number: 20230212431Abstract: The present invention relates to an ethylene-vinyl alcohol copolymer composition, a single-layer film and a multilayer structure containing the same. Said ethylene-vinyl alcohol copolymer composition includes an ethylene-vinyl alcohol copolymer, an antioxidant, and a fluorine-containing compound; and the ratio of the antioxidant content to the fluorine content is 0.5 to 65. Thereby, the film containing said ethylene-vinyl alcohol copolymer composition not only has good heat resistance, but also can avoid the situation that a large number of gels are generated during the preparation process.Type: ApplicationFiled: June 30, 2022Publication date: July 6, 2023Inventors: Shih Yuan Su, Hou Hsi Wu
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Patent number: 11664322Abstract: A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.Type: GrantFiled: September 21, 2020Date of Patent: May 30, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Ming Shih Yeh, Wei-Cheng Wu
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Publication number: 20230151287Abstract: A first voltage source produces a first voltage such as an AC voltage. Further, a first electrode of a hydrogen generation system conveys the first voltage. The first voltage conveyed over the first electrode generates low-temperature plasma extending between the first electrode and the mass of material. Presence of the low-temperature plasma releases gas from the mass of material.Type: ApplicationFiled: November 10, 2022Publication date: May 18, 2023Inventors: Juan Pablo Trelles, Hsi-Wu Wong, John Hunter Mack
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Patent number: 11652063Abstract: An embodiment is a structure including a first die having an active surface with a first center point, a molding compound at least laterally encapsulating the first die, and a first redistribution layer (RDL) including metallization patterns extending over the first die and the molding compound. A first portion of the metallization patterns of the first RDL extending over a first portion of a boundary of the first die to the molding compound, the first portion of the metallization patterns not extending parallel to a first line, the first line extending from the first center point of the first die to the first portion of the boundary of the first die.Type: GrantFiled: July 13, 2020Date of Patent: May 16, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu, Tsung-Shu Lin
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Patent number: 11646220Abstract: A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.Type: GrantFiled: February 14, 2022Date of Patent: May 9, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Ming Shih Yeh, Jing-Cheng Lin, Hung-Jui Kuo
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Publication number: 20230124804Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.Type: ApplicationFiled: December 19, 2022Publication date: April 20, 2023Inventors: Kuo-Chiang Ting, Chi-Hsi Wu, Shang-Yun Hou, Tu-Hao Yu, Chia-Hao Hsu, Ting-Yu Yeh
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Patent number: 11630538Abstract: An electronic device is provided. The electronic device includes an ultrasonic input module and a control unit. The control unit is electrically connected to the ultrasonic input module. The control unit is configured to: continuously read a setting signal of the ultrasonic input module within a preset time to generate a threshold, where the setting signal includes a plurality of sensing values; receive an input signal by using the ultrasonic input module, where the input signal includes a feature value; and compare the feature value with the threshold to generate associated information, and process the input signal according to the associated information. The disclosure further provides a touch method applied to the electronic device.Type: GrantFiled: November 1, 2021Date of Patent: April 18, 2023Assignee: ASUSTEK COMPUTER INC.Inventors: Wen Fang Hsiao, I-Hsi Wu, Tsung-Yi Lin
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Patent number: 11626296Abstract: A semiconductor device includes a first die extending through a molding compound layer, a first dummy die having a bottom embedded in the molding compound layer, wherein a height of the first die is greater than a height of the first dummy die, and an interconnect structure over the molding compound layer, wherein a first metal feature of the interconnect structure is electrically connected to the first die and a second metal feature of the interconnect structure is over the first dummy die and extends over a sidewall of the first dummy die.Type: GrantFiled: March 8, 2021Date of Patent: April 11, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Hsien-Wei Chen, Wei-Yu Chen
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Patent number: 11612057Abstract: A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.Type: GrantFiled: July 27, 2022Date of Patent: March 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Hsien Hsieh, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Hsien-Wei Chen, Li-Han Hsu, Wei-Cheng Wu
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Publication number: 20230085054Abstract: A semiconductor device includes a first electronic component, a second electronic component, a third electronic component, a plurality of first interconnection structures, and a plurality of second interconnection structures. The first electronic component is between the second and the third electronic components. The first interconnection structures are between the first and the second electronic components. Each first interconnection structures has a length along a first direction substantially parallel to a surface of the first electronic component, and a width along a second direction substantially parallel to the surface and substantially perpendicular to the first direction. The length is larger than the width. The second interconnection structures are between the second and the third electronic components, and electrically connected to the second and the third electronic components. A height of each second interconnection structure is different from a height of each first interconnection structure.Type: ApplicationFiled: November 20, 2022Publication date: March 16, 2023Inventors: WEIMING CHRIS CHEN, TU-HAO YU, KUO-CHIANG TING, SHANG-YUN HOU, CHI-HSI WU