Patents by Inventor Hsi Wu

Hsi Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11373969
    Abstract: An embodiment is a method including forming a first passive device in a first wafer, forming a first dielectric layer over a first side of the first wafer, forming a first plurality of bond pads in the first dielectric layer, planarizing the first dielectric layer and the first plurality of bond pads to level top surfaces of the first dielectric layer and the first plurality of bond pads with each other, hybrid bonding a first device die to the first dielectric layer and at least some of the first plurality of bond pads, and encapsulating the first device die in a first encapsulant.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: June 28, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Hsi Wu, Der-Chyang Yeh, Hsien-Wei Chen, Jie Chen
  • Patent number: 11355468
    Abstract: A method of manufacturing a semiconductor device structure includes forming a bond or joint between a first device and a second device. The first device comprises an integrated passive device (IPD) and a first contact pad disposed over the IPD. The second device comprises a second contact pad. The first contact pad has a first surface with first lateral extents. The second contact pad has a second surface with second lateral extents. The width of the second lateral extents is less than the width of the first lateral extents. The joint structure includes the first contact pad, the second contact pad, and a solder layer interposed therebetween. The solder layer has tapered sidewalls extending in a direction away from the first surface of the first contact pad to the second surface of the second contact pad. At least one of the first surface or the second surface is substantially planar.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ju Chen, An-Jhih Su, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Publication number: 20220165611
    Abstract: A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.
    Type: Application
    Filed: February 14, 2022
    Publication date: May 26, 2022
    Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Ming Shih Yeh, Jing-Cheng Lin, Hung-Jui Kuo
  • Patent number: 11342196
    Abstract: A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Chen-Hua Yu, Chi-Hsi Wu, Der-Chyang Yeh, An-Jhih Su, Wei-Yu Chen
  • Publication number: 20220137734
    Abstract: An electronic device is provided. The electronic device includes an ultrasonic input module and a control unit. The control unit is electrically connected to the ultrasonic input module. The control unit is configured to: continuously read a setting signal of the ultrasonic input module within a preset time to generate a threshold, where the setting signal includes a plurality of sensing values; receive an input signal by using the ultrasonic input module, where the input signal includes a feature value; and compare the feature value with the threshold to generate associated information, and process the input signal according to the associated information. The disclosure further provides a touch method applied to the electronic device.
    Type: Application
    Filed: November 1, 2021
    Publication date: May 5, 2022
    Inventors: Wen Fang HSIAO, I-Hsi WU, Tsung-Yi LIN
  • Publication number: 20220137714
    Abstract: An electronic device is provided. The electronic device includes a touch module, a motion sensor, a memory, and a control unit. The touch module is configured to generate a touch signal. The motion sensor is configured to detect motion of the electronic device to generate motion data. The memory stores a preset motion condition. The control unit is electrically connected to the touch module, the motion sensor, and the memory, and configured to: receive the motion data; and determine whether the motion data meets the preset motion condition or not, and generate a virtual touch signal when the motion data meets the preset motion condition. A control method applied to the electronic device is further provided.
    Type: Application
    Filed: October 29, 2021
    Publication date: May 5, 2022
    Inventors: Wen Fang HSIAO, I-Hsi WU, Shin-Yi HUANG
  • Publication number: 20220122952
    Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.
    Type: Application
    Filed: January 3, 2022
    Publication date: April 21, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Li-Hsien Huang, Po-Hao Tsai, Ming-Shih Yeh, Ta-Wei Liu
  • Patent number: 11287923
    Abstract: A control method of a handheld electronic device adapted to a handheld electronic device is provided. The handheld electronic device includes a touch panel. The control method includes the steps of: dividing the touch panel into two areas, and defining a trigger region in each area; configuring the touch panel to detect a touch point; and determining whether the touch point is located in the trigger region or not, and when the touch point is located in the trigger region, forming a shielding region corresponding to the trigger region; and when the touch point is not located in the trigger region, repeatedly detecting the touch point.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: March 29, 2022
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: I-Hsi Wu, Hsin-Yi Pu, Wen-Fang Hsiao
  • Publication number: 20220068880
    Abstract: The semiconductor structure includes a plurality of first dies, a plurality of second dies disposed over each of the first dies, and a dielectric material surrounding the plurality of first dies and the plurality of second die. Each of the second dies overlaps a portion of each first die.
    Type: Application
    Filed: November 12, 2021
    Publication date: March 3, 2022
    Inventors: CHEN-HUA YU, CHI-HSI WU, DER-CHYANG YEH, HSIEN-WEI CHEN, AN-JHIH SU, TIEN-CHUNG YANG
  • Publication number: 20220056491
    Abstract: A method of directly microbially converting a plant oil, an animal fat, free fatty acid, or a combination thereof to wax esters includes growing a yeast or bacterial strain in a medium comprising the plant oil, the animal fat, the free fatty acid, or combination thereof, under conditions suitable to produce the wax esters, wherein the yeast or bacterial strain is engineered to express a FAR gene encoding fatty acid alcohol reductase and a WS gene encoding a wax ester synthase, and optionally isolating the produced wax esters. Similar methods of directly microbially converting a plant oil, an animal fat, free fatty acid, or a combination thereof to omega-3 fatty acids by growing a microorganism in a medium comprising the plant oil, the animal fat, the free fatty acid, or combination thereof, under conditions suitable to produce omega-3 fatty acids are also described.
    Type: Application
    Filed: June 8, 2021
    Publication date: February 24, 2022
    Inventors: Dongming Xie, Ya-Hue Valerie Soong, Na Liu, Andrew Thomas Olson, Hsi-Wu Wong
  • Patent number: 11251071
    Abstract: A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: February 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Ming Shih Yeh, Jing-Cheng Lin, Hung-Jui Kuo
  • Patent number: 11240357
    Abstract: An electronic device is provided, which includes: a body; a camera module, rotatably disposed on the body; a motor, connected to the camera module, and configured to drive the camera module to rotate between a front camera position and a rear camera position relative to the body; a first direction sensor, disposed on the body and configured to provide a first sensing signal; a second direction sensor, disposed on the camera module and configured to provide a second sensing signal; and a processor, electrically connected to the motor, the first direction sensor, and the second direction sensor, and the processor is configured to control the motor based on the first sensing signal and the second sensing signal.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: February 1, 2022
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: I-Hsi Wu, Jen-Pang Hsu, Kai-Yu Shu, Yi-Yuan Lin
  • Patent number: 11217570
    Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Li-Hsien Huang, Po-Hao Tsai, Ming-Shih Yeh, Ta-Wei Liu
  • Patent number: 11201142
    Abstract: A semiconductor package includes a die, an insulation layer, a plurality of first electrical conductive vias, a plurality of second electrical conductive vias, a plurality of thermal conductive vias and a connecting pattern. The die includes a plurality of first pads and a plurality of second pads. The insulation layer is disposed on the die and includes a plurality of openings exposing the first pads and the second pads. The first electrical conductive vias and the second electrical conductive vias are disposed in the openings and contact the first pads and the second pads respectively. The thermal conductive vias are disposed on the insulation layer. The connecting pattern is disposed on the insulation layer and connects the first electrical conductive vias and the thermal conductive vias. The thermal conductive vias are connected to the first pads through the connecting pattern and the first electrical conductive vias.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: December 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Hsien Huang, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Hua-Wei Tseng, Ming-Chih Yew, Yi-Jen Lai, Ming-Shih Yeh
  • Publication number: 20210366814
    Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.
    Type: Application
    Filed: May 22, 2020
    Publication date: November 25, 2021
    Inventors: Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang, Chih-Ta Shen, Szu-Wei Lu, Ying-Ching Shih, Wen-Chih Chiou, Chi-Hsi Wu, Chen-Hua Yu
  • Publication number: 20210366805
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a die stack disposed over the substrate, a heat spreader disposed over the substrate and having a surface facing the substrate, and a thermal interface material (TIM) disposed between the die stack and the heat spreader. A bottommost die of the die stack includes a surface exposed from remaining dies of the die stack from a top view perspective; and the TIM is in contact with the exposed surface of the bottommost die and the surface of the heat spreader, and is in contact with a sidewall of at least one of the plurality of dies of the die stack.
    Type: Application
    Filed: August 6, 2021
    Publication date: November 25, 2021
    Inventors: CHI-HSI WU, WENSEN HUNG, TSUNG-SHU LIN, SHIH-CHANG KU, TSUNG-YU CHEN, HUNG-CHI LI
  • Patent number: 11183399
    Abstract: An interposer substrate is manufactured with a scribe line between adjacent regions. In an embodiment a separate exposure reticle is utilized to pattern the scribe line. The exposure reticle to pattern the scribe line will create an exposure region which overlaps and overhangs the exposure regions utilized to form adjacent regions.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: November 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hsin Wei, Hsien-Pin Hu, Shang-Yun Hou, Chi-Hsi Wu, Chen-Hua Yu, Wen-Jung Chuang, Chun-Che Chen, Jhih-Ming Lin, Chih-Ching Lin, Shih-Wen Huang, Chun Hua Chang, Tsung-Yang Hsieh
  • Patent number: 11177238
    Abstract: A semiconductor structure includes a plurality of first dies, a second die disposed over each of the first dies, and a dielectric material surrounding the first dies and the second die. The second dies overlaps a portion of each of the first dies. A dimension of the second die is different from a dimension of the first dies.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: November 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen-Hua Yu, Chi-Hsi Wu, Der-Chyang Yeh, Hsien-Wei Chen, An-Jhih Su, Tien-Chung Yang
  • Patent number: 11164855
    Abstract: A package structure includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipating element, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipating element connects to the first semiconductor die, and the first semiconductor die is between the circuit element and the heat dissipating element, where a sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipating element is substantially equal to a second thickness of the second semiconductor die. The insulating encapsulation encapsulates the first semiconductor die, the second semiconductor die and the heat dissipating element, wherein a surface of the heat dissipating element is substantially leveled with the insulating encapsulation.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: November 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Weiming Chris Chen, Chi-Hsi Wu, Chih-Wei Wu, Kuo-Chiang Ting, Szu-Wei Lu, Shang-Yun Hou, Ying-Ching Shih, Hsien-Ju Tsou, Cheng-Chieh Li
  • Patent number: 11164508
    Abstract: An electronic device is disclosed. The electronic device includes a display unit, a light sensor, and a processor. The display unit has a brightness value. The light sensor senses an ambient light to generate a light intensity signal. The processor is coupled to the display unit and the light sensor and accesses a program instruction from a memory to perform the following steps: continuously receiving the light intensity signal from the light sensor; smoothing a plurality of light intensity signals to generate a plurality of smoothing signals; and maintaining the brightness value of the display unit for a preset time period and then determining whether to adjust the brightness value when a difference generated by subtracting a previous smoothing signal of a target smoothing signal of the smoothing signals from the target smoothing signal is less than the first threshold or greater than the second threshold.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: November 2, 2021
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Chih-Hsien Yang, Chih-Chuan Lin, Kou-Liang Lin, Chi-Liang Tsai, I-Hsi Wu, Yu-Hao Hu