Abstract: A chemical mechanical polishing method is provided. The chemical mechanical polishing method includes steps of providing a plurality of semiconductor elements to be polished, obtaining a respective dimension of the each semiconductor element to be polished, and polishing the each semiconductor element according to the respective dimension thereof.

Abstract: A solar cell is provided that an extremely thin light absorber is formed between a n-type semiconductor layer and a p-type semiconductor layer such that the light absorber is used to absorb solar energy, while the p-type semiconductor layer may not absorb light. After separation of electrons and holes, the carriers will not recombine during the conduction, in order to avoid energy loss.

Abstract: A metal oxide semiconductor transistor includes a gate, a metal oxide active layer, a gate insulating layer, a source, and a drain. The metal oxide active layer has a first surface and a second surface, and the first surface faces to the gate. The gate insulating layer is disposed between the gate and the metal oxide active layer. The source and the drain are respectively connected to the metal oxide active layer. The second surface defines a mobility enhancing region between the source and the drain. An oxygen content of the metal oxide active layer in the mobility enhancing region is less than an oxygen content of the metal oxide active layer in the region outside the mobility enhancing region. The metal oxide semiconductor transistor has high carrier mobility.

Abstract: A vertical electro-optical component and a method for forming the same are provided. The vertical electro-optical component includes a substrate, a first electrode layer formed on the substrate, a patterned insulating layer formed on the first electrode layer, a metal layer formed on the patterned insulating layer, a semiconductor layer formed on the first electrode layer, and a second electrode layer formed on the semiconductor layer, wherein the semiconductor layer encapsulates the patterned insulating layer and the metal layer. The vertical electro-optical component thus has a low operational voltage of a vertical transistor and a high reaction speed of a photo diode, and may be used to form light-emitting transistors.

Abstract: A biochemical sensor and a method of manufacturing the same are disclosed. The biochemical sensor includes a substrate, a gate arranged on one side of the substrate, a gate insulating layer arranged on one side of the gate opposite to the substrate, an active layer arranged on one side of the gate insulating layer opposite to the gate, a source and a drain arranged on one side of the active layer opposite to the gate insulating layer, and a biochemical sensing layer arranged on one side of the active layer opposite to the gate insulating layer and between the source and the drain.

Abstract: A smart window includes a windowpane, at least one sensor and a wireless signal transceiver. The sensor is disposed on the windowpane and configured for detecting an environmental factor and accordingly outputting a sensing signal. The wireless signal transceiver is disposed on the windowpane and electrically connected to the sensor. The wireless signal transceiver is configured for further transmitting the sensing signal from the sensor. A smart window system includes the aforementioned smart window. The smart window and the smart window system adopt wireless communication manner to transmit the sensing signals, and thereby the smart window system has an overall modulation to an environmental factor.

Abstract: The instant disclosure relates to a metal oxide thin film transistor having a threshold voltage modification layer. The thin film transistor includes a gate electrode, a dielectric layer formed on the gate electrode, an active layer formed on the dielectric layer, a source electrode and a drain electrode disposed separately on the active layer, and a threshold voltage modulation layer formed on the active layer in direct contact with the back channel of the transistor. The threshold voltage modulation layer and the active layer have different work functions so that the threshold voltage modulation layer modulates the threshold voltage of devices and improve the performance of the transistor.

Abstract: The present invention provides a vertical type sensor, including a substrate; a first electrode formed on the substrate; a sensing layer formed on the first electrode layer and reactive to a target substance, wherein the first electrode layer is interposed between the substrate and the sensing layer; and a second electrode layer formed on the sensing layer and having a plurality of openings, wherein the sensing layer is interposed between the first electrode layer and the second electrode layer, and the target substance contacts the sensing layer via the plurality of openings. The vertical type sensor of the present invention provides instant, sensitive and rapid detection.

Abstract: A method of fabricating an organic thin film transistor is disclosed, which comprises steps of (S1) forming a gate electrode on a substrate; (S2) forming a gate insulating layer on the gate electrode; (S3) providing a gas on the surface of the gate insulating layer to form hydrophobic molecules on the surface of the gate insulating layer; (S4) forming an organic semiconductor layer, a source electrode, and a drain electrode over the gate insulating layer having hydrophobic molecules thereon, wherein the gas of step (S3) is at least one selected from the group consisting of halogen-substituted hydrocarbon, un-substituted hydrocarbon, and the mixtures thereof. The method of the present invention utilizes gases comprising carbon or fluorine atom to perform surface treatment on the surface of the gate insulating layer, therefore the hydrophobic character of the surface of the gate insulating layer can be enhanced and the electrical properties of the OTFT can be improved.

Abstract: A self-aligned top-gate thin film transistor and a fabrication method thereof. The method includes preparing a substrate having sequentially formed thereon an oxide semiconductor layer, a dielectric layer, and a metallic layer, wherein the oxide semiconductor layer includes first and second connecting regions that are not covered by the dielectric layer and the metallic layer thereon respectively, the first and second connecting regions having a property of a conductor after undergone a heating process or an ultraviolet irradiation; and a source electrode and a drain electrode formed on the substrate and connected to the first and second connecting regions, respectively. Therefore, the contact resistance of the first and second connecting regions can be reduced without the process of ion dopants as required by prior art techniques, thereby simplifying the manufacturing process. Also, the source electrode and the drain electrode can be exactly relocated and further increase performance of the device.

Abstract: A phototransistor includes a substrate, a gate layer, a dielectric layer, an active layer, a source and a drain, and a light absorption layer. The gate layer is disposed on a top of the substrate, and the dielectric layer is disposed on a top of the gate layer. The active layer has a first bandgap and is disposed on a top of the dielectric layer, and the source and the drain are disposed on a top of the active layer. The light absorption layer has a second bandgap and is capped on the active layer, and the second bandgap is smaller than the first bandgap.

Abstract: A vertical transistor and a method of fabricating the vertical transistor are provided. The vertical transistor has a substrate, a first electrode formed on the substrate, a first insulation layer formed on the first electrode, with a portion of the first electrode exposed from the first insulation layer and having a thickness greater than 50 nm and no more than 300 nm, a grid electrode formed on the first insulation layer, a semiconductor layer formed on the first electrode, and a second electrode formed on the semiconductor layer.

Abstract: A method for fabricating an organic light emitting diode and a device thereof are provided. The method includes: providing a substrate; dispensing to the substrate a second organic molecule solution resulting from dissolving a second organic molecule in a solvent; applying the second organic molecule solution to a surface of the substrate so as to form a wet film layer; and heating the wet film layer by a heating unit to remove the solvent therefrom and thereby form a second organic molecule film. The method is effective in fabricating a uniform multilayer structure for use in fabrication of large-area photoelectric components.

Abstract: A method for manufacturing a self-aligned thin-film transistor (TFT) is described. Firstly, an oxide gate, a dielectric layer, and a photoresist layer are deposited on a first surface of a transparent substrate in sequence. Then, an ultraviolet light is irradiated on a second surface of the substrate opposite to the first surface to expose the photoresist layer, in which a gate manufactured by the oxide gate serves as a mask, and absorbs the ultraviolet light irradiated on the photoresist layer corresponding to the oxide gate. Then, the exposed photoresist layer is removed, and a transparent conductive layer is deposited on the unexposed photoresist layer and the dielectric layer. Then, a patterning process is executed on the transparent conductive layer to form a source and a drain, and an active layer is formed to cover the source, the drain, and the dielectric layer, so as to finish a self-aligned TFT structure.

Abstract: A liquid crystal display apparatus comprises a system-on-glass (SOG) and a bandgap reference (BGR) circuit. The BGR circuit, which is formed on the SOG, comprises a current mirror set and a diode set. The current mirror set is configured to generate a plurality of fixed currents. The diode set, which is formed by a plurality of diode-connected thin film transistors (TFT), is configured to generate a BGR voltage according to the fixed currents.

Abstract: A patterning process is provided. The patterning process includes the following steps. First, a substrate is provided. Then, a patterned self-assembled monolayer (SAM) is formed on the substrate. Afterwards, an organic material layer is formed over the substrate to cover the self-assembled monolayer. Thereafter, a portion of the organic material layer is removed, wherein the organic material layer in contact with the patterned SAM is retained such that a patterned organic material layer.

Abstract: A method of forming a polysilicon thin film transistor. An amorphous silicon channel layer is formed over an insulating substrate. An active region is patterned out in the amorphous silicon channel layer. An oxide layer and a gate electrode are sequentially formed over the amorphous silicon channel layer. A lightly doped source/drain region is formed in the amorphous silicon channel layer and then a spacer is formed over the gate electrode. A source/drain region is formed in the amorphous silicon channel layer. A portion of the oxide layer above the source/drain region is removed. An isolation spacer is formed on the sidewalls of the spacer. A self-aligned silicide layer is formed at the top section of the spacer and the source/drain region. Finally, a metal-induced lateral crystallization process is conducted to transform the amorphous silicon channel layer into a lateral-crystallization-polysilicon channel layer.

Abstract: A method of forming a polysilicon thin film transistor. An amorphous silicon channel layer is formed over an insulating substrate. An active region is patterned out in the amorphous silicon channel layer. An oxide layer and a gate electrode are sequentially formed over the amorphous silicon channel layer. A lightly doped source/drain region is formed in the amorphous silicon channel layer and then a spacer is formed over the gate electrode. A source/drain region is formed in the amorphous silicon channel layer. A portion of the oxide layer above the source/drain region is removed. An isolation spacer is formed on the sidewalls of the spacer. A self-aligned silicide layer is formed at the top section of the spacer and the source/drain region. Finally, a metal-induced lateral crystallization process is conducted to transform the amorphous silicon channel layer into a lateral-crystallization-polysilicon channel layer.

Abstract: A method of forming a polysilicon thin film transistor. An amorphous silicon channel layer is formed over an insulating substrate. An active region is patterned out in the amorphous silicon channel layer. An oxide layer and a gate electrode are sequentially formed over the amorphous silicon channel layer. A lightly doped source/drain region is formed in the amorphous silicon channel layer and then a spacer is formed over the gate electrode. A source/drain region is formed in the amorphous silicon channel layer. A portion of the oxide layer above the source/drain region is removed. An isolation spacer is formed on the sidewalls of the spacer. A self-aligned silicide layer is formed at the top section of the spacer and the source/drain region. Finally, a metal-induced lateral crystallization process is conducted to transform the amorphous silicon channel layer into a lateral-crystallization-polysilicon channel layer.