Patents by Inventor Hsiao-Wen Zan

Hsiao-Wen Zan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200220084
    Abstract: Described herein are electronics that incorporate heterocyclic organic compounds. More specifically, described herein are organic electronics systems that are combined with donor-acceptor organic semiconductors, along with methods for making such devices, and uses thereof.
    Type: Application
    Filed: November 26, 2019
    Publication date: July 9, 2020
    Inventors: Mingqian He, Robert George Manley, Karan Mehrotra, Hsin-Fei Meng, Hsiao-Wen Zan
  • Publication number: 20200132618
    Abstract: A gas sensor includes a first electrode, a gas detecting layer disposed on the first electrode, and an electric-conduction enhanced electrode unit being electrically connected to the first electrode and the gas detecting layer. The electric-conduction enhanced electrode unit includes an electric-conduction enhancing layer and a second electrode electrically connected to the electric-conduction enhancing layer. The electric-conduction enhancing layer is electrically connected to the gas detecting layer and is made of an electrically conductive organic material.
    Type: Application
    Filed: July 18, 2019
    Publication date: April 30, 2020
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Hsiao-Wen ZAN, Hsin-Fei MENG, Yu-Chi LIN, Shang-Yu YU, Ting-Wei TUNG, Yi-Chu WU, Yu-Nung MAO
  • Patent number: 10326088
    Abstract: An organic thin film transistor includes a substrate, a hydrophobic layer, an oxide layer, a hydrophilic layer, a semiconductor layer, and a source/drain layer. The hydrophobic layer covers a surface of the substrate. The oxide layer is located on the hydrophobic layer and has plural segments. The hydrophilic layer is located on the segments of the oxide layer, and the oxide layer is located between the hydrophilic layer and the hydrophobic layer. The semiconductor layer is located on the hydrophilic layer, and the hydrophilic layer is located between the semiconductor layer and the oxide layer. The source/drain layer connects across the semiconductor layer on the segments of the oxide layer.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: June 18, 2019
    Assignee: E Ink Holdings Inc.
    Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Chun-Chih Chen, Hung-Chuan Liu, Zong-Xuan Li, Wei-Tsung Chen
  • Patent number: 10263089
    Abstract: A transistor including a substrate, a gate layer, a first insulating layer, an active layer, a source and a drain is provided. The gate layer is disposed on the first insulating layer, and has a plurality of first through holes. The first insulating layer covers the gate layer and a part of the substrate exposed by the first through holes, and forms a plurality of recesses respectively corresponding to the first through holes. The active layer is disposed on the first insulating layer, and has a plurality of second through holes. The second through holes communicate with the recesses, respectively. The source is disposed on a part of the active layer. The drain is disposed on another part of the active layer. A manufacturing method of the transistor is also provided.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: April 16, 2019
    Assignee: E Ink Holdings Inc.
    Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Chia-Wei Chou, Cheng-Hang Hsu
  • Publication number: 20190079040
    Abstract: A sensing element includes a conductive substrate, a zinc oxide seed layer, a plurality of zinc oxide nanorods, a film with an electrical double layer, and an organic sensing layer. The zinc oxide seed layer is located on the conductive substrate. The zinc oxide nanorods extend from the zinc oxide seed layer. The film with the electrical double layer covers the zinc oxide nanorods. The organic sensing layer is located on the film with the electrical double layer.
    Type: Application
    Filed: August 22, 2018
    Publication date: March 14, 2019
    Inventors: Hsiao-Wen ZAN, Chuang-Chuang TSAI, Yu-Nung MAO, Hung-Chuan LIU, Zong-Xuan LI, Wei-Tsung CHEN
  • Publication number: 20180350923
    Abstract: A transistor including a substrate, a source, a drain, an active portion, a fin-shaped gate, and an insulation layer is provided. The source is located on the substrate. The drain is located on the substrate. The active portion connects the source and the drain. The fin-shaped gate wraps the active portion. A first portion of the insulation layer separates the fin-shaped gate from the active portion, a second portion of the insulation layer separates the fin-shaped gate from the substrate, a third portion of the insulation layer separates the fin-shaped gate from the source and from the drain, and a fourth portion of the insulation layer is located on a surface of the fin-shaped gate facing away from the active portion. Here, the insulation layer is integrally formed.
    Type: Application
    Filed: August 8, 2018
    Publication date: December 6, 2018
    Applicant: E Ink Holdings Inc.
    Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Hsin Chiao, Wei-Tsung Chen
  • Publication number: 20180294155
    Abstract: Processes for obtaining a semiconductor nanodevice comprising a substrate, onto which patterned metal-oxide thin films having semiconductor properties are deposited, are provided, as well as semiconductor devices comprising them. The present invention belongs to the field of semiconductor nanodevices.
    Type: Application
    Filed: May 3, 2016
    Publication date: October 11, 2018
    Inventors: Olivier Soppera, Hsiao-Wen Zan, Hung-Cheng Lin, Chang-Hung Li, Fabrice Stehlin, Arnaud Spangenberg, Fernand Wleder, Chung-Chen Yeh
  • Publication number: 20180294422
    Abstract: An organic thin film transistor includes a substrate, a hydrophobic layer, an oxide layer, a hydrophilic layer, a semiconductor layer, and a source/drain layer. The hydrophobic layer covers a surface of the substrate. The oxide layer is located on the hydrophobic layer and has plural segments. The hydrophilic layer is located on the segments of the oxide layer, and the oxide layer is located between the hydrophilic layer and the hydrophobic layer. The semiconductor layer is located on the hydrophilic layer, and the hydrophilic layer is located between the semiconductor layer and the oxide layer. The source/drain layer connects across the semiconductor layer on the segments of the oxide layer.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 11, 2018
    Inventors: Hsiao-Wen ZAN, Chuang-Chuang TSAI, Chun-Chih CHEN, Hung-Chuan LIU, Zong-Xuan LI, Wei-Tsung CHEN
  • Patent number: 10079283
    Abstract: A manufacturing method of a transistor is provided, and the method includes: providing a base; forming a fin-shaped gate on the base; covering the fin-shaped gate with an insulation layer; providing a substrate; forming a partially cured sol-gel on the substrate; inserting the fin-shaped gate into the partially cured sol-gel, so that a portion of the fin-shaped gate is uncovered by the partially cured sol-gel; after inserting the fin-shaped gate into the partially cured sol-gel, curing the partially cured sol-gel; and processing a portion of the partially cured sol-gel not overlapping with the fin-shaped gate to increase conductivity of the portion of the partially cured sol-gel.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 18, 2018
    Assignee: E Ink Holdings Inc.
    Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Hsin Chiao, Wei-Tsung Chen
  • Patent number: 10026919
    Abstract: An organic light-emitting device includes a first electrode, a first light-emitting layer, a first low work function layer, a second low work function layer, a conductive etching-resistant layer, a first hole-injection layer, a second light-emitting layer, and a second electrode. The first light-emitting layer is disposed over the first electrode. The first low work function layer is disposed over the first light-emitting layer. The second low work function layer is disposed over the first low work function layer, and a work function of the second low work function layer is greater than a work function of the first low work function layer. The conductive etching-resistant layer is disposed over the second low work function layer. The first hole-injection layer is disposed over the conductive etching-resistant layer. The second light-emitting layer is disposed over the first hole-injection layer. The second electrode is disposed over the second light-emitting layer.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: July 17, 2018
    Assignee: E Ink Holdings Inc.
    Inventors: Hsin-Fei Meng, Sheng-Fu Horng, Hsiao-Wen Zan, Hao-Wen Chang, Cheng-Hang Hsu
  • Publication number: 20180128762
    Abstract: A sensitive device includes a plurality of first conductive nanostructures, a conductive layer and at least one electrode. The conductive layer covers the first conductive nanostructures. An intrinsic melting point of the conductive layer is higher than that of the first conductive nanostructures. At least one of the conductive layer and the first conductive nanostructures is sensitive to gas. The electrode is electrically connected to at least one of the first conductive nanostructures and the conductive layer.
    Type: Application
    Filed: September 12, 2017
    Publication date: May 10, 2018
    Inventors: Hsiao-Wen ZAN, Chuang-Chuang TSAI, Po-Yi CHANG, Hung-Chuan LIU, Yi-Ting CHOU, Wei-Tsung CHEN
  • Publication number: 20180076402
    Abstract: A method of forming a transistor includes: forming a stack structure including a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer on a substrate; patterning the first insulating layer, the second conductive layer, and the second insulating layer to form at least one opening passing through the first insulating layer, the second conductive layer, and the second insulating layer; forming a semiconductor layer over the second insulating layer and filling the opening; removing the portion of the semiconductor layer over the second insulating layer, in which the portion of the semiconductor layer filled in the opening constitutes at least one semiconductor channel; and forming a third conductive layer over the semiconductor channel.
    Type: Application
    Filed: April 5, 2017
    Publication date: March 15, 2018
    Inventors: Hsiao-Wen ZAN, Shao-Fu PENG, Cheng-Hang HSU
  • Patent number: 9917268
    Abstract: A method of forming a transistor includes: forming a stack structure including a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer on a substrate; patterning the first insulating layer, the second conductive layer, and the second insulating layer to form at least one opening passing through the first insulating layer, the second conductive layer, and the second insulating layer; forming a semiconductor layer over the second insulating layer and filling the opening; removing the portion of the semiconductor layer over the second insulating layer, in which the portion of the semiconductor layer filled in the opening constitutes at least one semiconductor channel; and forming a third conductive layer over the semiconductor channel.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: March 13, 2018
    Assignee: E Ink Holdings Inc.
    Inventors: Hsiao-Wen Zan, Shao-Fu Peng, Cheng-Hang Hsu
  • Publication number: 20180069188
    Abstract: An organic light-emitting device includes a first electrode, a first light-emitting layer, a first low work function layer, a second low work function layer, a conductive etching-resistant layer, a first hole-injection layer, a second light-emitting layer, and a second electrode. The first light-emitting layer is disposed over the first electrode. The first low work function layer is disposed over the first light-emitting layer. The second low work function layer is disposed over the first low work function layer, and a work function of the second low work function layer is greater than a work function of the first low work function layer. The conductive etching-resistant layer is disposed over the second low work function layer. The first hole-injection layer is disposed over the conductive etching-resistant layer. The second light-emitting layer is disposed over the first hole-injection layer. The second electrode is disposed over the second light-emitting layer.
    Type: Application
    Filed: August 31, 2017
    Publication date: March 8, 2018
    Inventors: Hsin-Fei MENG, Sheng-Fu HORNG, Hsiao-Wen ZAN, Hao-Wen CHANG, Cheng-Hang HSU
  • Patent number: 9748482
    Abstract: A semiconductor sensing device that includes a nanowire conductive layer, a semiconductor sensing layer, and a conductive layer is provided. The nanowire conductive layer includes a plurality of connected conductive nanowires, and gaps are formed between the conductive nanowires. The semiconductor sensing layer is electrically connected to the nanowire conductive layer. The conductive layer is electrically connected to the semiconductor sensing layer. The semiconductor sensing layer is located between the nanowire conductive layer and the conductive layer. A manufacturing method of a semiconductor sensing device is also provided.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: August 29, 2017
    Assignee: E Ink Holdings Inc.
    Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Pei-Chen Yu, Ming-Yen Chuang, Chia-Chun Yeh
  • Patent number: 9647138
    Abstract: A metal oxide semiconductor transistor includes a gate, a metal oxide active layer, a gate insulating layer, a source, and a drain. The metal oxide active layer has a first surface and a second surface, and the first surface faces to the gate. The gate insulating layer is disposed between the gate and the metal oxide active layer. The source and the drain are respectively connected to the metal oxide active layer. The second surface defines a mobility enhancing region between the source and the drain. An oxygen content of the metal oxide active layer in the mobility enhancing region is less than an oxygen content of the metal oxide active layer in the region outside the mobility enhancing region. The metal oxide semiconductor transistor has high carrier mobility.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: May 9, 2017
    Assignee: E INK HOLDINGS INC.
    Inventors: Chuang-Chuang Tsai, Hsiao-Wen Zan, Hsin-Fei Meng, Chun-Cheng Yeh
  • Publication number: 20170018616
    Abstract: A manufacturing method of a transistor is provided, and the method includes: providing a base; forming a fin-shaped gate on the base; covering the fin-shaped gate with an insulation layer; providing a substrate; forming a partially cured sol-gel on the substrate; inserting the fin-shaped gate into the partially cured sol-gel, so that a portion of the fin-shaped gate is uncovered by the partially cured sol-gel; after inserting the fin-shaped gate into the partially cured sol-gel, curing the partially cured sol-gel; and processing a portion of the partially cured sol-gel not overlapping with the fin-shaped gate to increase conductivity of the portion of the partially cured sol-gel.
    Type: Application
    Filed: September 30, 2016
    Publication date: January 19, 2017
    Applicant: E Ink Holdings Inc.
    Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Hsin Chiao, Wei-Tsung Chen
  • Publication number: 20170012227
    Abstract: An active device is disposed on a substrate and includes a gate, an organic active layer, a gate insulation layer, a plurality of crystal induced structures, a source and a drain. The gate insulation layer is disposed between the gate and the organic active layer. The crystal induced structures distribute in the organic active layer and directly contact with the substrate or the gate insulation layer. The source and the drain are disposed on two opposite sides of the organic active layer, wherein a portion of the organic active layer is exposed between the source and the drain.
    Type: Application
    Filed: April 12, 2016
    Publication date: January 12, 2017
    Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Chao-Hsuan Chen, Cheng-Hang Hsu
  • Patent number: 9368634
    Abstract: A thin film transistor (TFT) including a gate, a dielectric layer, a metal-oxide semiconductor channel, a source, and a drain is provided. The gate and the metal-oxide semiconductor channel are overlapped. The gate, the source, and the drain are separated by the dielectric layer. Besides, the source and the drain are respectively located on two opposite sides of the metal-oxide semiconductor channel. The metal-oxide semiconductor channel includes a metal-oxide semiconductor layer and a plurality of nano micro structures disposed in the metal-oxide semiconductor layer and separated from one another. In another aspect, a display panel including the TFT and a method of fabricating the TFT are also provided.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 14, 2016
    Assignee: E Ink Holdings Inc.
    Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Xue-Hung Tsai, Henry Wang, Wei-Tsung Chen
  • Patent number: 9331294
    Abstract: A vertical electro-optical component and a method for forming the same are provided. The vertical electro-optical component includes a substrate, a first electrode layer formed on the substrate, a patterned insulating layer formed on the first electrode layer, a metal layer formed on the patterned insulating layer, a semiconductor layer formed on the first electrode layer, and a second electrode layer formed on the semiconductor layer, wherein the semiconductor layer encapsulates the patterned insulating layer and the metal layer. The vertical electro-optical component thus has a low operational voltage of a vertical transistor and a high reaction speed of a photo diode, and may be used to form light-emitting transistors.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: May 3, 2016
    Assignee: National Chiao Tung University
    Inventors: Hsiao-Wen Zan, Hsin-Fei Meng, Wu-Wei Tsai, Yu-Chiang Chao