Abstract: A nanoparticle conjugate includes a quantum dot (QD) and a thermally activated delayed fluorescence (TADF) molecule bound to the QD. In some instances, the TADF molecule can be directly bound to a surface of the QD. In other instances, the TADF molecule can be indirectly bound to the QD via an interaction with one or more capping ligands disposed on a surface of the QD. Nanoparticle conjugates described herein can be incorporated into emissive layers of electroluminescent light-emitting diode devices to yield electroluminescent quantum dot-containing light-emitting diode (QD-LED) devices.

Abstract: Among other things, planning a motion of a machine having moving capabilities is based on strategic guidelines derived from various basic principles, such as laws, ethics, preferences, driving experiences, and road environments.

Abstract: A method includes forming a semiconductor fin over a substrate; forming first, second, and third gate structures crossing the semiconductor fin; forming first and second epitaxial source/drain structures on opposite sides of the first gate structure, and forming third and fourth source/drain epitaxial structures on opposite sides of the third gate structure; forming first gate spacers, second gate spacers, third gate spacers on opposite sidewalls of the first, second, and third gate structures, respectively; forming a first hard mask over the first, second, and third gate structures; patterning the first hard mask to form a first opening; etching a portion of the second gate structure and a portion of the semiconductor fin through the first opening to form a recess; and forming a dielectric layer in the recess, in which a dielectric constant of the dielectric layer is lower than a dielectric constant of silicon oxide.

Abstract: The present disclosure relates to compounds of Formula (I)-(V) as compounds capable of emitting delayed fluorescence and uses of these compounds in organic light-emitting diodes.

Abstract: A layer of carbon (e.g., graphite or graphene) at a metal interface (e.g., between an MEOL interconnect and a gate contact or a source or drain region contact, between an MEOL contact plug and a BEOL metallization layer, and/or between BEOL conductive structures) is used to reduce contact resistance at the metal interface, which increases electrical performance of an electronic device. Additionally, in some implementations, the layer of carbon may help prevent heat transfer from a second metal to a first metal when the second metal is deposited over the first metal. This results in more symmetric deposition of the second metal, which reduces surface roughness and contact resistance at the metal interface. As an alternative, in some implementations, the layer of carbon is etched before deposition of the second metal in order to reduce contact resistance at the metal interface.

Abstract: A deposition apparatus and a method are provided. A method includes placing a substrate over a platform in a chamber of a deposition system. A precursor material is introduced into the chamber. A first gas curtain is generated in front of a first electromagnetic (EM) radiation source coupled to the chamber. A plasma is generated from the precursor material in the chamber, wherein the plasma comprises dissociated components of the precursor material. The plasma is subjected to a first EM radiation from the first EM radiation source. The first EM radiation further dissociates the precursor material. A layer is deposited over the substrate. The layer includes a reaction product of the dissociated components of the precursor material.

Abstract: Methods of forming vias for coupling source/drain regions to backside interconnect structures in semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a conductive feature adjacent a gate structure; a dielectric layer on the conductive feature and the gate structure; a metal via embedded in the dielectric layer; and a liner layer between and in contact with the metal via and the dielectric layer, the liner layer being boron nitride.

Abstract: A method for forming a semiconductor device includes providing a base device having a top dielectric layer, forming a sacrificial layer on the top dielectric layer, and patterning the sacrificial layer to form openings. The method also includes depositing first protective dielectric layer and a low-K dielectric layer in the opening and performing planarization to form a first planarized structure including sacrificial regions and low k regions separated by a first protective layer. Next, top portions of the low-k dielectric layer are replaced with a second protective dielectric layer to form a second planarized structure that includes enclosed dielectric structures separated by sacrificial regions. The method further includes replacing the remaining portions of the sacrificial layer with a target metal interconnect material to form a third planarized structure that includes metal interconnect material disposed between enclosed dielectric structures.

Abstract: In a method of manufacturing a semiconductor device, a metal gate structure is formed and cut into two pieces of metal gate structures by forming a gate end spaces. A first liner layer is formed in the gate end space, and a sacrificial layer is formed on the first liner layer, and recessed. A second liner layer is formed over the recessed sacrificial layer, an air gap is formed by removing the recessed sacrificial layer; and a third liner layer is formed over the second liner layer.

Abstract: Techniques in accordance with embodiments described herein are directed to a MFM structure that includes a resistance component, an inductance component and a capacitance component. The MFM device is equivalent to a series LC circuit with the resistance component coupled in parallel with the capacitance component. The MFM structure is used as a series LC resonant circuit, band-pass circuit, band-stop circuit, low-pass filter, high-pass filter, oscillators, or negative capacitors.

Abstract: A method of forming a semiconductor device includes forming a source/drain region over a substrate; forming a first interlayer dielectric over the source/drain region; forming a gate structure over the substrate and laterally adjacent to the source/drain region; and forming a gate mask over the gate structure, the forming the gate mask comprising: etching a portion of the gate structure to form a recess relative to a top surface of the first interlayer dielectric; depositing a first dielectric layer over the gate structure in the recess and over the first interlayer dielectric; etching a portion of the first dielectric layer; depositing a semiconductor layer over the first dielectric layer in the recess; and planarizing the semiconductor layer to be coplanar with the first interlayer dielectric. In another embodiment, the method further includes forming a gate spacer over the substrate, wherein the etching the portion of the gate structure further comprises etching a portion of the gate spacer.

Abstract: The present disclosure relates to compounds of Formula (I) and (II): as compounds capable of emitting delayed fluorescence, and uses of the compounds in organic light-emitting diodes.

Abstract: An improved method of forming conductive features and a semiconductor device formed by the same are disclosed. Methods for forming under-bump metallurgy (UBM) structures having different surface profiles and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a first dielectric layer over an integrated circuit device; forming a first conductive feature in the first dielectric layer; selectively depositing a polymer layer over the first conductive feature; selectively depositing an etch stop layer over the first dielectric layer adjacent the polymer layer; removing the polymer layer to form a first opening; and forming a second conductive feature in the first opening and electrically coupled to the first conductive feature.

Abstract: A compound represented by the following general formula is used as a light emitting material. Any one of R1, R2 and R4 is a hydrogen atom or a deuterium atom, the remaining ones are donor groups but at least one is a carbazol-9-yl group condensed with a benzofuran ring, a benzothiophene ring, an indole ring, an indene ring or a silaindene ring.

Abstract: Techniques in accordance with embodiments described herein are directed to a MFM structure that includes a resistance component, an inductance component and a capacitance component. The MFM device is equivalent to a series LC circuit with the resistance component coupled in parallel with the capacitance component. The MFM structure is used as a series LC resonant circuit, band-pass circuit, band-stop circuit, low-pass filter, high-pass filter, oscillators, or negative capacitors.

Abstract: A conversion control circuit controls a power stage circuit of a switching power converter according to a first feedback signal and a second feedback signal, wherein the conversion control circuit includes an error amplifier circuit, a ramp signal generation circuit, a pulse width modulation circuit, and a quick response control circuit. The quick response control circuit performs a quick response control function, wherein the quick response control function includes: comparing the second feedback signal with at least one reference threshold to generate a quick response control signal; and when the second feedback signal crosses the reference threshold, adjusting a slope of a ramp signal according to the quick response control signal to accelerate an increase or decrease of the duty of a PWM signal, thereby accelerating the transient response of the switching power converter.

Abstract: To provide an excellent light emitting material. A compound represented by the following general formula is used as the light emitting material. R is a hydrogen atom, a deuterium atom, an aryl group, or a heteroaryl group bonding via a carbon atom, Ar is an aryl group, or a heteroaryl group bonding via a carbon atom, D1 and D2 each are a donor group, and at least one is a hetero ring-condensed carbazol-9-yl group.

Abstract: A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.

Abstract: A bracket includes a fixing seat, an adapter seat, a first clamping block, a second clamping block, a first clamping piece, a second clamping piece, a main screw and a position-limiting element. The fixing seat includes a first protrusion post. The adapter seat includes a second protrusion post. The first clamping block includes a first through-hole and a first pivot hole. The second clamping block including a first tapped hole and a second pivot hole. The first clamping piece includes a first clamping part and a first pivotal shaft. The first pivotal shaft is inserted into the first pivot hole. The second clamping piece includes a second clamping part and a second pivotal shaft. The second pivotal shaft is inserted into the second pivot hole. The main screw is penetrated through the first through-hole and then tightened into the second tapped hole.