Abstract: Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.

Abstract: Disclosed herein are novel synthetic polypeptides and uses thereof in the preparation of liposomes. According to embodiments of the present disclosure, the synthetic polypeptide comprises a membrane lytic motif, a masking motif, and a linker configured to link the membrane lytic motif and the masking motif. The linker is cleavable by a stimulus, such as, light, protease, or phosphatase. Once being coupled to a liposome, the exposure to the stimulus cleaves the linker that results in the separation of the masking motif from the membrane lytic motif, which in turn exerts membrane lytic activity on the liposome that leads to the collapse of the intact structure of the liposome, and releases the agent encapsulated in the liposome to the target site. Also disclosed herein are methods of diagnosing or treating a disease in a subject by use of the present liposomes.

Abstract: A method of manufacturing a solid granule for use as or in a cleaning agent includes providing an anionic surfactant component having at least one anionic sulfonate surfactant and at least one anionic fatty alcohol-based sulfate surfactant; providing a granule-forming agent; mixing the anionic surfactant component and the granule-forming agent into a solid mixture; receiving the solid mixture in a granulation device, the granulation device having a first roller cutter and a second roller cutter, the first roller cutter includes a plurality of first blades and a plurality of first grooves, the second roller cutter having a plurality of second blades and a plurality of second grooves; cutting the solid mixture into a rough granule by cooperating the first blades with the second blades; and polishing the rough granule into the solid granule by friction rubbing between the first grooves and the second grooves.

Abstract: A method of manufacturing a semiconductor device includes forming a gate trench over a semiconductor substrate, depositing a gate dielectric layer and a work function layer in the gate trench, depositing a capping layer over the work function layer, passivating a surface portion of the capping layer to form a passivation layer, removing the passivation layer, depositing a fill layer in the gate trench, recessing the fill layer and the capping layer, and forming a contact metal layer above the capping layer in the gate trench.

Abstract: A semiconductor package device includes a flexible carrier, a first chip, a second chip, a first molding layer, a first adhesive layer and a second molding layer. The flexible carrier has a flexible layer and a rigid layer. The flexible layer has a patterned build-up circuit. The rigid layer is connected to a portion surface of the flexible layer. The position that the flexible layer connected to the rigid layer is formed a first carrying part and a second carrying part. The region of the flexible layer between the first carrying part and the second carrying part without the rigid layer is formed as a first flexible part. The first chip is connected to the first carrying part by flip-chip manner and the second chip is connected to the second carrying part by flip-chip manner. The first molding layer covers the first chip and the second molding layer covers the second chip. The first adhesive layer is connected between the first molding layer and the second carrying part.

Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.

Abstract: A method of making a semiconductor device, includes: forming a first molding layer on a substrate; forming a first plurality of vias in the first molding layer; forming a first conductive line over the first molding layer, wherein the first conductive line is laterally disposed over the first molding layer and a first end of the conductive line aligns with and is electrically coupled to a first via of the first plurality of vias; forming a second molding layer above the first molding layer; and forming a second plurality of vias in the second molding layer, wherein a second via of the second plurality of vias aligns with and is electrically coupled to a second end of the conductive line, and wherein the second plurality of vias, the conductive line, and the first plurality of vias are electrically coupled to one another.

Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.

Abstract: Provided is a semiconductor device including a first n-type transistor comprising a first work function layer, the first work function layer comprising a first underlying layer; and a second n-type transistor comprising a second work function layer, the second work function layer comprising a second underlying layer. The first and second underlying layers each comprises a metal nitride layer with at least two kinds of metals, and a thickness of the first underlying layer is greater than a thickness of the second underlying layer. A method of manufacturing a gate structure for a semiconductor device is also provided.

Abstract: A fingerprint identification module includes a light guiding member, a flexible circuit board, two light emitting members, and a fingerprint identification chip. The light guiding member includes a bottom and a protruding edge. The protruding edge surrounds to form a first space. A first through-hole is formed on the bottom. The flexible circuit board is disposed in the first space and has a first portion, a second portion, a third portion, and a fourth portion connected in sequence. The first portion goes out of the light guiding member through the first through-hole. The third portion faces a direction opposite to the bottom. The second portion and the fourth portion face the bottom of the light guiding member. The light emitting members are disposed on the flexible circuit board and face the light guiding member. The fingerprint identification chip is disposed on the third portion of the flexible circuit board.

Abstract: Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.

Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.

Abstract: A test strip for sampling a bodily fluid may include multiple layers of a substrate material, an adhesive between at least some of the multiple layers, and a microfluidic channel formed between at least some of the multiple layers. The test strip may further include multiple electrodes on one of the multiple layers, positioned and partially exposed within the microfluidic channel, an additional material positioned at or near an entrance to the microfluidic channel, to selectively limit the flow of at least one of bubbles or debris into the microfluidic channel, and at least one exit port in at least one of the multiple layers to allow for release of pressure from the test strip. In some embodiments, the test strip is a saliva analysis test strip. In some embodiments, the test strip includes multiple exit ports to prevent blockage of sample flow.

Abstract: A method of assessing a bodily fluid sample on a test strip may involve applying a periodic signal with a first electrode located at a first location in a microfluidic channel of the test strip, monitoring the applied periodic signal with a second electrode located at a second location in the microfluidic channel, and using a third electrode located at a third location in the microfluidic channel as a reference electrode. The method may also include: collecting the bodily fluid sample in the microfluidic channel; continuing to apply the periodic signal, monitor the periodic signal and use the third electrode as a reference electrode while collecting the bodily fluid sample; and determining that the bodily fluid sample is sufficient for analyzing, based at least in part on the applied and monitored periodic signal.

Abstract: An intelligent analysis system for measuring signals of polishing pad surface, a method and a computer readable medium thereof are provided. The intelligent analysis system includes a measurement signal capturing device and a measurement signal analysis device signally-connected to each other. After the measurement signal capturing device obtains the measurement signal of the measured polishing pad, an artificial intelligence model of the measurement signal analysis device is trained to classify the measurement signal to remove the interference caused by a water film on the polishing pad to obtain a better measurement signal, such that the intelligent analysis system can solve the problems of time-consuming, laborious and misjudgment caused by the classification of the measurement signal by the conventional technology.

Abstract: Monocyte-specific nucleic acid aptamers and lipid nanoparticles comprising such for use in drug delivery. Also disclosed herein are use of the aptamer-based lipid nanoparticle drug delivery system for treating heart injury.

Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.

Abstract: A key structure is provided, including a housing, a shaft body, a first magnetic component and a second magnetic component. The housing has a bottom portion and a top portion which are opposite to each other, and has a first opening located at the top portion. The shaft body is coupled with the housing by passing through the first opening, and the shaft body is suitable for being pressed to move in a pressing direction from the top portion to the bottom portion. The first magnetic component is arranged on the shaft body. The second magnetic component is arranged on the housing. The first magnetic component and the second magnetic component are separated by the housing.