Patents by Inventor Hsien Ming

Hsien Ming has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11088257
    Abstract: Provided is a semiconductor device including a first n-type fin field effect transistor (FinFET) and a second n-type FinFET. The first FinFET includes a first work function layer. The first work function layer includes a first portion of a first layer. The second n-type FinFET includes a second work function layer. The second work function layer includes a second portion of the first layer and a first portion of a second layer underlying the second portion of the first layer. A thickness of the first work function layer is less than a thickness of the second work function layer. A method of manufacturing the semiconductor device is also provided.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Fen Chien, Hsiao-Kuan Wei, Hsien-Ming Lee, Chin-You Hsu
  • Publication number: 20210242081
    Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.
    Type: Application
    Filed: May 27, 2020
    Publication date: August 5, 2021
    Inventors: Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Pin-Hsuan Yeh, Wei-Chin Lee, Hsien-Ming Lee, Chien-Hao Chen, Chi On Chui
  • Publication number: 20210239586
    Abstract: A method of assessing a bodily fluid sample on a test strip may involve applying a periodic signal with a first electrode located at a first location in a microfluidic channel of the test strip, monitoring the applied periodic signal with a second electrode located at a second location in the microfluidic channel, and using a third electrode located at a third location in the microfluidic channel as a reference electrode. The method may also include: collecting the bodily fluid sample in the microfluidic channel; continuing to apply the periodic signal, monitor the periodic signal and use the third electrode as a reference electrode while collecting the bodily fluid sample; and determining that the bodily fluid sample is sufficient for analyzing, based at least in part on the applied and monitored periodic signal.
    Type: Application
    Filed: January 27, 2021
    Publication date: August 5, 2021
    Inventors: Efstratios Skafidas, Hsien Ming, You Liang, Duc Huynh, Thanh Nguyen, Michael Erlichster
  • Patent number: 11081396
    Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: August 3, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Jyun Wu, Hung-Chi Wu, Chia-Ching Lee, Pin-Hsuan Yeh, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen, Sheng-Liang Pan, Huan-Just Lin
  • Patent number: 11075124
    Abstract: The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: July 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Da-Yuan Lee, Hung-Chin Chung, Hsien-Ming Lee, Kuan-Ting Liu, Syun-Ming Jang, Weng Chang, Wei-Jen Lo
  • Publication number: 20210225788
    Abstract: Present disclosure provides a semiconductor structure and a method for fabricating a semiconductor structure. The semiconductor structure includes a substrate, a conductive layer in the substrate, a conductive bump over the substrate and electrically coupled to the conductive layer, and a dielectric stack, including a polymer layer laterally surrounding the conductive bump and including a portion spaced from a nearest outer edge of the conductive bump with a gap, wherein a first thickness of the polymer layer in a first region is greater than a second thickness of the polymer layer in a second region adjacent to the first region, a first bottom surface of the polymer layer in the first region is leveled with a second bottom surface of the polymer layer in the second region, and a dielectric layer underneath the polymer layer.
    Type: Application
    Filed: April 7, 2021
    Publication date: July 22, 2021
    Inventors: CHANG-PIN HUANG, TUNG-LIANG SHAO, HSIEN-MING TU, CHING-JUNG YANG, YU-CHIA LAI
  • Patent number: 11056395
    Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: July 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen, Ching-Hwanq Su
  • Patent number: 11024505
    Abstract: Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiao-Kuan Wei, Hsien-Ming Lee, Chin-You Hsu, Hsin-Yun Hsu, Pin-Hsuan Yeh
  • Publication number: 20210146501
    Abstract: Disclosed are a detection method and a detection apparatus for a polishing pad of a chemical mechanical polishing device, particularly a detection method and a detection apparatus for detecting a surface of a polishing pad dynamically. An isolation region isolated by a gas to expose the polishing pad is formed by the detecting device, and a detection is performed on the isolation region, such that the chemical mechanical polishing device is capable of detecting the polishing pad without interrupting a manufacturing process and the detection results with more accurate can be achieved. Thereby, the polishing pad can be repaired and replaced more timely.
    Type: Application
    Filed: November 9, 2020
    Publication date: May 20, 2021
    Applicant: Ta Liang Technology Co., Ltd.
    Inventors: Hsien-Ming Lee, Chun-Chen Chen, Ching-Tang Hsueh, Po-Ching Huang
  • Patent number: 10998414
    Abstract: Methods for forming semiconductor structures are disclosed herein. An exemplary method includes forming a gate structure having a dummy gate stack over a substrate, performing a gate replacement process, such that the dummy gate stack is replaced with a metal gate stack, and forming a non-silane based oxide capping layer over the gate structure. The gate replacement process includes removing a portion of the dummy gate stack from the gate structure, thereby forming a gate trench. A work function layer is formed in the gate trench, a blocking layer is formed in the gate trench over the work function layer, and a metal layer (including, for example, aluminum) is formed in the gate trench over the blocking layer. The blocking layer includes titanium and nitrogen with a titanium to nitrogen ratio that is greater than one. In some implementations, the work function layer is formed over a dielectric layer.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Chin Chung, Shiang-Rung Tsai, Hsien-Ming Lee, Cheng-Lung Hung, Hsiao-Kuan Wei
  • Patent number: 10985121
    Abstract: Present disclosure provides a semiconductor structure, including a substrate, a pad on the substrate, a conductive layer electrically coupled to the pad at one end, a metal bump including a top surface and a sidewall, a solder bump on the top surface of the metal bump, a dielectric layer surrounding the sidewall of the metal bump and having a top surface, and the top surface of the metal bump entirely protruding the top surface of the dielectric layer, and a polymer layer on the top surface of the dielectric layer, the polymer layer being spaced from both the sidewall of the metal bump and a nearest outer edge of the solder bump with a gap. A method for fabricating a semiconductor device is also provided.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: April 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chang-Pin Huang, Tung-Liang Shao, Hsien-Ming Tu, Ching-Jung Yang, Yu-Chia Lai
  • Publication number: 20210111027
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.
    Type: Application
    Filed: December 21, 2020
    Publication date: April 15, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yu LIN, Chi-Yu CHOU, Hsien-Ming LEE, Huai-Tei YANG, Chun-Chieh WANG, Yueh-Ching PAI, Chi-Jen YANG, Tsung-Ta TANG, Yi-Ting WANG
  • Publication number: 20210082849
    Abstract: A semiconductor device includes a substrate includes a first layer and a second layer over the first layer, a bump disposed over the second layer, a molding disposed over the second layer and surrounding the bump, and a retainer disposed over the second layer, wherein the retainer is disposed between the molding and a periphery of the substrate. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing several bumps on the substrate, disposing a retainer on the substrate and surrounding the bumps, and disposing a molding between the bumps and the retainer.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 18, 2021
    Inventors: TUNG-LIANG SHAO, YU-CHIA LAI, HSIEN-MING TU, CHANG-PIN HUANG, CHING-JUNG YANG
  • Publication number: 20210083118
    Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 18, 2021
    Inventors: Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen
  • Publication number: 20210082768
    Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.
    Type: Application
    Filed: September 12, 2019
    Publication date: March 18, 2021
    Inventors: Shao-Jyun Wu, Hung-Chi Wu, Chia-Ching Lee, Pin-Hsuan Yeh, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen, Sheng-Liang Pan, Huan-Just Lin
  • Publication number: 20210057280
    Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Inventors: Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen, Ching-Hwanq Su
  • Publication number: 20210046606
    Abstract: A method for repairing a polishing pad in real time includes a trimming step, a detection step, and a reconstruction and analysis step. A surface morphology of the polishing pad is reconstructed through detection, and analysis is performed according to the reconstruction, to ensure that a surface of the polishing pad can recover its function after the surface of the polishing pad is trimmed, so that the polishing pad can be used effectively to reduce costs.
    Type: Application
    Filed: August 13, 2020
    Publication date: February 18, 2021
    Applicant: Ta Liang Technology Co., Ltd.
    Inventors: Chao-Chang Chen, Jian-Shian Lin, Chun-Chen Chen, Jen-Chien Li, Hsien-Ming Lee, Ching-Tang Hsueh
  • Publication number: 20210043521
    Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.
    Type: Application
    Filed: October 12, 2020
    Publication date: February 11, 2021
    Inventors: Ya-Wen Chiu, Da-Yuan Lee, Hsien-Ming Lee, Kai-Cyuan Yang, Yu-Sheng Wang, Chih-Hsiang Fan, Kun-Wa Kuok
  • Publication number: 20210007646
    Abstract: A test strip for sampling a bodily fluid may include multiple layers of a substrate material, an adhesive between at least some of the multiple layers, and a microfluidic channel formed between at least some of the multiple layers. The test strip may further include multiple electrodes on one of the multiple layers, positioned and partially exposed within the microfluidic channel, an additional material positioned at or near an entrance to the microfluidic channel, to selectively limit the flow of at least one of bubbles or debris into the microfluidic channel, and at least one exit port in at least one of the multiple layers to allow for release of pressure from the test strip. In some embodiments, the test strip is a saliva analysis test strip. In some embodiments, the test strip includes multiple exit ports to prevent blockage of sample flow.
    Type: Application
    Filed: July 9, 2020
    Publication date: January 14, 2021
    Inventors: Thanh Cong Nguyen, Efstratios Skafidas, Duc Hau Huynh, Michael Erlichster, Duc Phuong Nguyen, Hsien Ming, Gursharan Chana, Ting Ting Lee, Chathurika Darshani Abeyrathne, You Liang, Trevor John Kilpatrick, Michael Luther, Alan Dayvault Luther
  • Publication number: 20210005322
    Abstract: A method of measuring an analyte in a bodily fluid sample and combining measurement data from multiple users may involve initiating a wireless connection between a handheld analyzer and a smart computing device on which an analyte analysis application has been downloaded and inserting a test strip into the handheld analyzer. The method may further involve collecting a sample of a bodily fluid on the test strip, measuring, with the handheld analyzer, a concentration of at least one analyte in the sample, wirelessly communicating the measured concentration from the handheld analyzer to the smart computing device, and displaying the measured concentration on the smart computing device. Finally, the method may involve transmitting the measured concentration to a database and organizing data including the measured concentration and at least one additional measured analyte concentration from at least one additional user on the database.
    Type: Application
    Filed: July 1, 2020
    Publication date: January 7, 2021
    Inventors: Duc Hau Huynh, Michael Erlichster, Thanh Cong Nguyen, Duc Phuong Nguyen, Efstratios Skafidas, Hsien Ming, Gursharan Chana, Ting Ting Lee, Chathurika Darshani Abeyrathne, You Liang, Trevor John Kilpatrick, Michael Luther, Alan Dayvault Luther