Patents by Inventor Hsien Ming
Hsien Ming has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11633834Abstract: A method for repairing a polishing pad in real time includes a trimming step, a detection step, and a reconstruction and analysis step. A surface morphology of the polishing pad is reconstructed through detection, and analysis is performed according to the reconstruction, to ensure that a surface of the polishing pad can recover its function after the surface of the polishing pad is trimmed, so that the polishing pad can be used effectively to reduce costs.Type: GrantFiled: August 13, 2020Date of Patent: April 25, 2023Assignee: TA LIANG TECHNOLOGY CO., LTD.Inventors: Chao-Chang Chen, Jian-Shian Lin, Chun-Chen Chen, Jen-Chien Li, Hsien-Ming Lee, Ching-Tang Hsueh
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Publication number: 20230122022Abstract: A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.Type: ApplicationFiled: December 20, 2022Publication date: April 20, 2023Inventors: Kuan-Chang Chiu, Chia-Ching Lee, Chien-Hao Chen, Hung-Chin Chung, Hsien-Ming Lee, Chi On Chui, Hsuan-Yu Tung, Chung-Chiang Wu
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Patent number: 11610982Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.Type: GrantFiled: January 4, 2021Date of Patent: March 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Hsiang Fan, Tsung-Han Shen, Jia-Ming Lin, Wei-Chin Lee, Hsien-Ming Lee, Chi On Chui
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Patent number: 11554154Abstract: This invention relates to a method of treating Major depressive disorder by orally administering to a subject a composition containing a Radix Polygalae (Polygala tenuifolia Willd) extract (PDC-1421). A solid dosage form of PDC-1421 can be prepared into the gelatin capsule. The oral administration of PDC-1421 in healthy volunteers was safe and well-tolerated for the daily dose from 380 mg to 3800 mg. The composition can be administered chronically over at least 25 days; the daily dose is administered once per day, twice per day, or three times per day, wherein each dose is 380-760 mg of the botanical extraction.Type: GrantFiled: July 22, 2020Date of Patent: January 17, 2023Assignee: BIOLITE, INC.Inventors: Chi-Hsin Richard King, Hsien-Ming Wu, Howard Doong, Tsung-Shann Jiang
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Patent number: 11545363Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.Type: GrantFiled: December 21, 2020Date of Patent: January 3, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yu Lin, Chi-Yu Chou, Hsien-Ming Lee, Huai-Tei Yang, Chun-Chieh Wang, Yueh-Ching Pai, Chi-Jen Yang, Tsung-Ta Tang, Yi-Ting Wang
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Patent number: 11538805Abstract: A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.Type: GrantFiled: November 4, 2020Date of Patent: December 27, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuan-Chang Chiu, Chia-Ching Lee, Chien-Hao Chen, Hung-Chin Chung, Hsien-Ming Lee, Chi On Chui, Hsuan-Yu Tung, Chung-Chiang Wu
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Patent number: 11532509Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.Type: GrantFiled: May 27, 2020Date of Patent: December 20, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Pin-Hsuan Yeh, Wei-Chin Lee, Hsien-Ming Lee, Chien-Hao Chen, Chi On Chui
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Publication number: 20220379433Abstract: Provided is a dressing device for a carrier. The dressing device comprises a dresser, a swing arm, a base and at least one damper. A first end and a second end of the swing arm are coupled to the dresser and the base, respectively, and the at least one damper is disposed inside the swing arm. Any axial vibration of the dresser or the swing arm during dressing for the carrier can be compensated or attenuated by the damper in an active manner properly, so as to make the surface of the carrier flatter and more uniform, which not only improves a removal rate of material and a polishing result of the surface in the subsequent chemical mechanical planarization process, but also prolongs the service life of the carrier. The present disclosure further relates to a polishing system for dressing the carrier by using the said dressing device.Type: ApplicationFiled: May 26, 2022Publication date: December 1, 2022Inventors: Chao-Chang Chen, Jen-Chieh Li, Cheng-Hsi Chuang, Shih-Chung Hsu, Yu-Tung Tsai, Hsien-Ming Lee, Chun-Chen Chen, Ching-Tang Hsueh
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Publication number: 20220367261Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.Type: ApplicationFiled: July 20, 2022Publication date: November 17, 2022Inventors: Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Pin-Hsuan Yeh, Wei-Chin Lee, Hsien-Ming Lee, Chien-Hao Chen, Chi On Chui
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Patent number: 11499124Abstract: A solid granule or granular material used for cleaning agents includes an anionic surfactant component and a molding agent. The anionic surfactant component includes an anionic sulfonate surfactant and an anionic fatty alcohol-based sulfate surfactant. Based on the total amount of the cleaning granule being 100 wt %, the combined amount of the sulfonate surfactant and the sulfate surfactant is between 15.0 wt % and 100 wt %. The amount of molding agent is 5.0 wt % or less. The ratio of the sulfonate surfactant to the sulfate surfactant is 0.20 to 0.75, inclusive. A cohesion of the solid granule is between 1000 g/mm and 4000 g/mm.Type: GrantFiled: July 15, 2020Date of Patent: November 15, 2022Assignee: YFY Consumer Products, Co.Inventors: Yi-Da Ho, Hsien-Ming Kwo, Hsing-Nan Chen, Shiu-Chih Tsai
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Publication number: 20220359296Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.Type: ApplicationFiled: July 21, 2022Publication date: November 10, 2022Inventors: Chia-Ching Lee, Hsin-Han Tsai, Shih-Hang Chiu, Tsung-Ta Tang, Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Da-Yuan Lee, Jian-Hao Chen, Chien-Hao Chen, Kuo-Feng Yu, Chia-Wei Chen, Chih-Yu Hsu
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Patent number: 11491608Abstract: Disclosed are a detection method and a detection apparatus for a polishing pad of a chemical mechanical polishing device, particularly a detection method and a detection apparatus for detecting a surface of a polishing pad dynamically. An isolation region isolated by a gas to expose the polishing pad is formed by the detecting device, and a detection is performed on the isolation region, such that the chemical mechanical polishing device is capable of detecting the polishing pad without interrupting a manufacturing process and the detection results with more accurate can be achieved. Thereby, the polishing pad can be repaired and replaced more timely.Type: GrantFiled: November 9, 2020Date of Patent: November 8, 2022Assignee: Ta Liang Technology Co., Ltd.Inventors: Hsien-Ming Lee, Chun-Chen Chen, Ching-Tang Hsueh, Po-Ching Huang
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Patent number: 11469200Abstract: A semiconductor device includes a substrate includes a first layer and a second layer over the first layer, a bump disposed over the second layer, a molding disposed over the second layer and surrounding the bump, and a retainer disposed over the second layer, wherein the retainer is disposed between the molding and a periphery of the substrate. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing several bumps on the substrate, disposing a retainer on the substrate and surrounding the bumps, and disposing a molding between the bumps and the retainer.Type: GrantFiled: November 30, 2020Date of Patent: October 11, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tung-Liang Shao, Yu-Chia Lai, Hsien-Ming Tu, Chang-Pin Huang, Ching-Jung Yang
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Patent number: 11437280Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.Type: GrantFiled: June 12, 2020Date of Patent: September 6, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Ching Lee, Hsin-Han Tsai, Shih-Hang Chiu, Tsung-Ta Tang, Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Da-Yuan Lee, Jian-Hao Chen, Chien-Hao Chen, Kuo-Feng Yu, Chia-Wei Chen, Chih-Yu Hsu
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Publication number: 20220238715Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.Type: ApplicationFiled: April 11, 2022Publication date: July 28, 2022Inventors: Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen
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Publication number: 20220208984Abstract: A method of forming a semiconductor device includes forming a gate electrode in a wafer. The formation of the gate electrode includes depositing a work-function layer, after the work-function layer is deposited, performing a treatment on the wafer, wherein the treatment is performed by soaking the wafer using a silicon-containing gas; after the treatment, forming a metal capping layer over the work-function layer; and depositing a filling metal over the metal capping layer.Type: ApplicationFiled: March 21, 2022Publication date: June 30, 2022Inventors: Tsung-Ta Tang, Yi-Ting Wang, Chung Ta Chen, Hsien-Ming Lee
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Publication number: 20220184167Abstract: This invention relates to a method of treating Attention-Deficit Hyperactivity Disorder by orally administering to a subject a composition containing a Radix Polygalae (Polygala tenuifolia Willd) extract (such as PDC-1421). A solid dosage form of the composition can be prepared into the gelatin capsule. The oral administration of the composition in healthy volunteers was safe and well-tolerated for the daily dose from 380 mg to 3800 mg. The composition can be administered chronically over at least 25 days; the daily dose is administered once per day, twice per day, or three times per day, wherein each dose is 380-760 mg of the botanical extract.Type: ApplicationFiled: December 14, 2020Publication date: June 16, 2022Inventors: Chi-Hsin Richard KING, Hsien-Ming WU, Howard DOONG, Tsung-Shann JIANG
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Patent number: 11359906Abstract: A system and a method for uniformed surface measurement are provided, in which a sensor is provided to perform measurements on a carrier in a polishing machine, and a measuring trajectory of the sensor on the carrier is adjusted by controlling the pivoting of a sensor carrier carrying the sensor and the rotation of a rotating platform in the polishing machine in order to achieve uniformed surface measurements of the carrier and real-time constructions of the surface topography. This allows the polishing state of the carrier to be monitored in real time, thereby improving the efficiency of the polishing process. A sensing apparatus for uniformed surface measurement is also provided.Type: GrantFiled: May 29, 2020Date of Patent: June 14, 2022Assignee: TA LIANG TECHNOLOGY CO., LTD.Inventors: Chao-Chang Chen, Jen-Chieh Li, Yong-Jie Ciou, Hsien-Ming Lee, Jian-Shian Lin, Chun-Chen Chen, Ching-Tang Hsueh
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Publication number: 20220173048Abstract: A semiconductor package device includes a flexible carrier, a first chip, a second chip, a first molding layer, a first adhesive layer and a second molding layer. The flexible carrier has a flexible layer and a rigid layer. The flexible layer has a patterned build-up circuit. The rigid layer is connected to a portion surface of the flexible layer. The position that the flexible layer connected to the rigid layer is formed a first carrying part and a second carrying part. The region of the flexible layer between the first carrying part and the second carrying part without the rigid layer is formed as a first flexible part. The first chip is connected to the first carrying part by flip-chip manner and the second chip is connected to the second carrying part by flip-chip manner. The first molding layer covers the first chip and the second molding layer covers the second chip. The first adhesive layer is connected between the first molding layer and the second carrying part.Type: ApplicationFiled: November 29, 2021Publication date: June 2, 2022Inventors: Chun-Hsien Yu, Shih-Ping Hsu, Hsien-Ming Tsai
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Publication number: 20220151926Abstract: Disclosed herein are novel synthetic polypeptides and uses thereof in the preparation of liposomes. According to embodiments of the present disclosure, the synthetic polypeptide comprises a membrane lytic motif, a masking motif, and a linker configured to link the membrane lytic motif and the masking motif. The linker is cleavable by a stimulus, such as, light, protease, or phosphatase. Once being coupled to a liposome, the exposure to the stimulus cleaves the linker that results in the separation of the masking motif from the membrane lytic motif, which in turn exerts membrane lytic activity on the liposome that leads to the collapse of the intact structure of the liposome, and releases the agent encapsulated in the liposome to the target site. Also disclosed herein are methods of diagnosing or treating a disease in a subject by use of the present liposomes.Type: ApplicationFiled: January 28, 2022Publication date: May 19, 2022Applicant: Academia SinicaInventors: Hsien-Ming LEE, Hua-De GAO, Jia-Lin HONG, Chih-Yu KUO, Cheng-Bang JIAN