Abstract: An automatic fluid replacement device is adapted to be mounted on an opening of a storage barrel. The automatic fluid replacement device includes a robotic arm, at least one fluid convey joint and a controller. The robotic arm has a gripper. The fluid convey joint includes a convey pipe, a sleeve and a sealing bag. The convey pipe is configured to deliver a fluid. The sleeve is sleeved on the convey pipe. The gripper clamps the sleeve. The sealing bag is sleeved on the sleeve. The controller is configured for automatically controlling the robotic arm to move the fluid convey joint into the opening and controlling the sealing bag to be inflated to seal the opening.

Abstract: A computing system performs artificial-intelligence (AI) super-resolution (SR). The computing system includes multiple processors, which further includes a graphics processing unit (GPU) and an AI processing unit (APU). The computing system also includes a memory to store AI models. When detecting an indication that the loading of the GPU exceeds a threshold, the processors reduce the resolution of a video output from the GPU in response to the indication. One of the AI models is selected based on graphics scenes in the video and the respective power consumption estimates of the AI models. The processors then perform AI SR operations on the video using the selected AI model to restore the resolution of the video for display.

Abstract: An airflow heating module for an equipment front-end module, including: a first perforated plate including a first plurality of holes used as airflow inlets; a second perforated plate including a second plurality of holes used as airflow outlets; a plurality of heaters provided between the first and the second perforated plates; and an active air intake device provided on the first perforated plate to accelerate airflow flowing through the first plurality of holes and past the plurality of heaters, such that the airflow carries heat generated by the heaters and passes through the second plurality of holes. Each of the heaters includes a heating tube and a fin. The fin is formed helically around the heating tube and attached thereto.

Abstract: A memory device includes a plurality of memory cells disposed over a substrate and formed as an array that has a plurality of rows and a plurality of columns. Each of the plurality of memory cells includes a plurality of transistors. A first subset of the plurality of memory cells, that are disposed in first neighboring ones of the plurality of rows, are physically coupled to a corresponding one of a plurality of second interconnect structures that carries a supply voltage through a corresponding one of a plurality of first interconnect structures. The plurality of first interconnect structures extend along a first lateral direction in parallel with a lengthwise direction of a channel of each of the transistors of the memory cells, and the plurality of second interconnect structures, disposed above the plurality of first interconnect structures, extend along a second lateral direction perpendicular to the first lateral direction.

Abstract: A display panel includes a circuit substrate, light emitting elements, a side wire, and a chip-on-film package structure. The circuit substrate includes a circuit structure located on a first surface. The side wire includes a first bonding portion disposed on the first surface of the circuit substrate and bonded to the circuit structure, a first extension portion, a second extension portion, and a second bonding portion that are sequentially connected and have the same resistivity. The first extension portion is disposed on a side surface of the circuit substrate. The second extension portion is disposed on a second surface of the circuit substrate and overlapped with a peripheral region. The second bonding portion is disposed on the second surface of the circuit substrate. An orthogonal projection of the second bonding portion is overlapped with a display region. The chip-on-film package structure is bonded to the second bonding portion.

Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor is of a first type in a first layer and includes a gate extending in a first direction and a first active region extending in a second direction perpendicular to the first direction. The second transistor is of a second type arranged in a second layer over the first layer and includes the gate and a second active region extending in the second direction. The semiconductor device further includes a first conductive line in a third layer between the first and second layers. The first conductive line electrically connects a first source/drain region of the first active region to a second source/drain region of the second active region. The gate comprises an intermediate portion disposed between the first active region and the second active region, wherein the first conductive line crosses the gate at the intermediate portion.

Abstract: In some embodiments, the present disclosure relates an integrated chip including a substrate. A conductive interconnect feature is arranged over the substrate. The conductive interconnect feature has a base feature portion with a base feature width and an upper feature portion with an upper feature width. The upper feature width is narrower than the base feature width such that the conductive interconnect feature has tapered outer feature sidewalls. An interconnect via is arranged over the conductive interconnect feature. The interconnect via has a base via portion with a base via width and an upper via portion with an upper via width. The upper via width is wider than the base via width such that the interconnect via has tapered outer via sidewalls.

Abstract: Examples disclosed herein relate to device. The device includes a substrate, a plurality of adjacent pixel-defining layer (PDL structures disposed over the substrate, and a plurality of sub-pixels. The PDL structure have a top surface coupled to adjacent sidewalls of the PDL structure. The plurality of sub-pixels are defined by the PDL structures. Each sub-pixel includes an anode, an organic light emitting diode (OLED), a cathode, and an encapsulation layer. The organic light emitting diode (OLED) material disposed over the anode. The OLED material extends over the top surface of the PDL structure past the adjacent sidewalls. The cathode is disposed over the OLED material. The cathode extends over the top surface of the PDL structure past the adjacent sidewalls. The encapsulation layer is disposed over the cathode. The encapsulation layer has a first sidewall and a second sidewall.

Abstract: The present disclosure relates to a complex probiotic composition and a method for improving exercise performance of a subject with low intrinsic aerobic exercise capacity. The complex probiotic composition, which includes Lactobacillus rhamnosus GKLC1, Bifidobacterium lactis GKK24 and Clostridium butyricum GKB7, administered to the subject with the low intrinsic aerobic exercise capacity in a continuation period, can effectively reduce serum lactic acid and serum urea nitrogen after aerobic exercise, reduce proportion of offal fat and/or increase liver and muscle glycogen contents, thereby being as an effective ingredient for preparation of various compositions.

Abstract: A script creation method for robot process automation and an electronic device using the same are provided. The electronic device includes an area defining unit, a recording unit, an analysis unit and a creation unit. The area defining unit is configured to obtain a recording area of a screen. The recording unit is configured to record a video according to the recording area. The analysis unit is configured to analyze a plurality of actions according to the video. The creation unit is configured to build a plurality of steps of a script according to the actions.

Abstract: A method for wireless communication performed by a user equipment (UE) is provided. The method includes receiving, from a base station (BS), a Radio Resource Control (RRC) configuration to configure a first semi-persistent scheduling (SPS) physical downlink shared channel (PDSCH) and generating first uplink control information (UCI) in response to the first SPS PDSCH, where the RRC configuration includes a first parameter that indicates a priority of the first UCI.

Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a masking structure with first openings over a semiconductor substrate and correspondingly forming metal layers in the first openings. The method also includes recessing the masking structure to form second openings between the metal layers and forming a sacrificial layer surrounded by a first liner in each of the second openings. In addition, after forming a second liner over the sacrificial layer in each of the second openings, the method includes removing the sacrificial layer in each of the second openings to form a plurality of air gaps therefrom.

Abstract: A method and a User Equipment (UE) for beam operations are provided. The method includes monitoring at least one of a plurality of Control Resource Sets (CORESETs) configured for the UE within an active Bandwidth Part (BWP) of a serving cell in a time slot; and applying a first Quasi Co-Location (QCL) assumption of a first CORESET of a set of one or more of the monitored at least one of the plurality of CORESETs to receive a Downlink (DL) Reference Signal (RS), wherein the first CORESET is associated with a monitored search space configured with a lowest CORESET Identity (ID) among the set of one or more of the monitored at least one of the plurality of CORESETs.

Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an annealing operation is performed on the fin structure. In the patterning of the semiconductor layer, a damaged area is formed on a sidewall of the fin structure, and the annealing operation eliminates the damaged area.

Abstract: A package structure including a first die, a second die, a dielectric body, a conductive terminal, a circuit layer and a patterned insulating layer is provided. The second die is disposed on the first die. A second active surface of the second die faces a first active surface of the first die. The dielectric body covers the first die. The conductive terminal is disposed on the dielectric body and opposite to the second die. The circuit layer includes a first circuit portion and a second circuit portion. The first circuit portion penetrates the dielectric body. The first die is electrically connected to the conductive terminal through the first circuit portion. The second circuit portion is embedded in the dielectric body. The second die is electrically connected to the first die through the second circuit portion. The patterned insulating layer covers the circuit layer and is embedded in the dielectric body.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip may comprise a first metal line disposed over a substrate. A via may be disposed directly over a top of the first metal line and the via may comprise a first lower surface and a second lower surface above the first lower surface. A first dielectric structure may be disposed laterally adjacent to the first metal line and may be disposed along a sidewall of the first metal line. A first protective etch-stop structure may be disposed directly over a top of the first dielectric structure and the first protective etch-stop structure may vertically separate the second lower surface of the via from the top of the first dielectric structure.

Abstract: A vacuum battery structural assembly and a vacuum multi-cell battery module composed thereof are provided and include a first repeating unit including a first frame plate and a second frame plate with respect to the first frame plate; and an electrolyte channel defined within the first frame plate and the second frame plate to accommodate a liquid electrolyte, wherein both a surface of the first frame plate and a surface of the second frame plate include a vacuum suction area, the vacuum suction area includes a vacuum aperture and a vacuum channel, wherein the vacuum aperture is formed on at least one surface of the first frame plate and the second frame plate, the vacuum channel is positioned inside the first frame plate and the second frame plate, and is configured to generate a longitudinal pressing suction force and seal the first frame plate and the second frame plate.

Abstract: A fixing structure used to connect a display panel to a housing of an electronic device during manufacture of the electronic device includes a fixing member, an auxiliary member spaced apart from the fixing member, and supporting posts disposed between the fixing member and the auxiliary member. The fixing member is to be bonded to the display panel. A projection of an outer edge of the auxiliary member on a plane of the fixing member is outside of an outer edge of the fixing member. The supporting posts and the auxiliary member are removed after the display panel is bonded to the fixing member. A method for assembling the display panel with the fixing structure is also disclosed.

Abstract: An epitaxial structure including a first epitaxial layer, a second epitaxial layer, and an interface treatment layer is provided. The first epitaxial layer is an ohmic contact layer. The second epitaxial layer is disposed on the first epitaxial layer and is a phosphide compound layer, where a material of the second epitaxial layer is different from a material of the first epitaxial layer. The interface treatment layer contacts the first epitaxial layer and the second epitaxial layer and is located between the first epitaxial layer and the second epitaxial layer. An image contrast ratio of a transmission electron microscope (TEM) of the interface treatment layer to the first epitaxial layer and an image contrast ratio of the TEM of the interface treatment layer to the second epitaxial layer are both greater than 1.005. A method for forming an epitaxial structure is also provided.

Abstract: An epitaxial structure includes a first epitaxial layer, a second epitaxial layer, and an interface treatment layer. The second epitaxial layer is disposed on the first epitaxial layer. The interface treatment layer is located between the first epitaxial layer and the second epitaxial layer and is in contact with the first epitaxial layer and the second epitaxial layer. The first epitaxial layer, the second epitaxial layer, and the interface treatment layer include the same material. An image contrast ratio of a transmission electron microscope (TEM) of the interface treatment layer to the first epitaxial layer and an image contrast ratio of a TEM of the interface treatment layer to the second epitaxial layer are both greater than 1.005. A method for forming an epitaxial structure is also provided.