Patents by Inventor Hsin-An Lin

Hsin-An Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ANTI-PD-1/CD47 BISPECIFIC ANTIBODY AND USE THEREOF
    Publication number: 20240084012
    Abstract: An isolated bispecific antibody or antigen-binding portion thereof includes a first chain which specifically binds to human PD-1(hPD-1) and blocks the interaction between hPD-1 and PD-L1, and a second chain which specifically binds to human CD47 and inhibits its interaction with SIRP-alpha, where the first chain and the second chain are coupled in a knob-in-hole format through their respective CH3 domain.
    Type: Application
    Filed: December 31, 2021
    Publication date: March 14, 2024
    Inventors: Chun-Jen LIN, Cheng-Chi CHAO, Chang-Hsin Chen, Gloria Guohong ZHANG, Guochen YAN
  • SEMICONDUCTOR INTERCONNECTION STRUCTURE AND METHODS OF FORMING THE SAME
    Publication number: 20240088023
    Abstract: An interconnect structure includes a dielectric layer, a first conductive feature, a hard mask layer, a conductive layer, and a capping layer. The first conductive feature is disposed in the dielectric layer. The hard mask layer is disposed on the first conductive feature. The conductive layer includes a first portion and a second portion, the first portion of the conductive layer is disposed over at least a first portion of the hard mask layer, and the second portion of the conductive layer is disposed over the dielectric layer. The hard mask layer and the conductive layer are formed by different materials. The capping layer is disposed on the dielectric layer and the conductive layer.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Inventors: Shao-Kuan LEE, Kuang-Wei YANG, Cherng-Shiaw TSAI, Cheng-Chin LEE, Ting-Ya LO, Chi-Lin TENG, Hsin-Yen HUANG, Hsiao-Kang CHANG, Shau-Lin SHUE
  • WIDE CHANNEL DIODE STRUCTURE INCLUDING SUB-FIN
    Publication number: 20240088132
    Abstract: An integrated circuit structure includes a sub-fin having (i) a first portion including a p-type dopant and (ii) a second portion including an n-type dopant. A first body of semiconductor material is above the first portion of the sub-fin, and a second body of semiconductor material is above the second portion of the sub-fin. In an example, the first portion of the sub-fin and the second portion of the sub-fin are in contact with each other, to form a PN junction of a diode. For example, the first portion of the sub-fin is part of an anode of the diode, and wherein the second portion of the sub-fin is part of a cathode of the diode.
    Type: Application
    Filed: September 13, 2022
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Nicholas A. Thomson, Kalyan C. Kolluru, Ayan Kar, Chu-Hsin Liang, Benjamin Orr, Biswajeet Guha, Brian Greene, Chung-Hsun Lin, Sabih U. Omar, Sameer Jayanta Joglekar
  • SEMICONDUCTOR SUBSTRATE BONDING TOOL AND METHODS OF OPERATION
    Publication number: 20240087915
    Abstract: A bonding tool includes a gas supply line that may extend directly between valves associated with one or more gas supply tanks and a processing chamber such that gas supply line is uninterrupted without any intervening valves or other types of structures that might otherwise cause a pressure buildup in the gas supply line between the processing chamber and the valves associated with the one or more gas supply tanks. The pressure in the gas supply line may be maintained at or near the pressure in the processing chamber so that gas provided to the processing chamber through the gas supply line does not cause a pressure imbalance in the processing chamber, which might otherwise cause early or premature contact between semiconductor substrates that are to be bonded in the processing chamber.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Yen-Hao HUANG, Chun-Yi CHEN, I-Shi WANG, Yin-Tun CHOU, Yuan-Hsin CHI, Sheng-Yuan LIN
  • SEMICONDUCTOR STRUCTURE AND METHOD MAKING THE SAME
    Publication number: 20240088025
    Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 14, 2024
    Inventors: Hsin-Yen Huang, Kai-Fang Cheng, Chi-Lin Teng, Hai-Ching Chen, Tien-I Bao
  • Self Timed Level Shifter Circuit
    Publication number: 20240088897
    Abstract: Systems and methods are provided for a level shifter. A level shifter includes a network of transistors configured to receive a signal at a first node in a first voltage domain and to generate a corresponding signal at a second node in a second voltage domain during a transition period of time. A self timing circuit is configured to receive an initiation signal based on the signal at the first node and to generate a voltage transition accelerator signal that is used to pull up the second node prior to the expiration of the transition period of time.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Wan-Yen Lin, Tsung-Hsin Yu
  • SEMICONDUCTOR WAFER PROCESSING TOOL WITH IMPROVED LEAK CHECK
    Publication number: 20240084445
    Abstract: A leak check is performed on a semiconductor wafer processing tool that includes a process chamber and process gas lines, and a semiconductor wafer is processed using the semiconductor wafer processing tool if the leak check passes. Each gas line includes a mass flow controller (MFC) and normally closed valves including an upstream and downstream valves upstream and downstream of the MFC. Leak checking includes: leak checking up to the downstream valves of the gas lines with the upstream valves closed and the downstream valves of the gas lines closed; and leak checking up to the upstream valve of each the process gas line with the upstream valves of the of the process gas lines closed and with the downstream valve of the of the process gas line being leak checked open and the downstream valve of every other process gas line closed.
    Type: Application
    Filed: January 4, 2023
    Publication date: March 14, 2024
    Inventors: Chih-Wei Chou, Yuan-Hsin Chi, Chih-Hao Yang, Hung-Chih Wang, Yu-Chi Liu, Sheng-Yuan Lin
  • ANTENNA STRUCTURE
    Publication number: 20240088561
    Abstract: An antenna structure is provided. The antenna structure includes a first metal layer and a second metal layer disposed over the first metal layer. The second metal layer forms a first antenna resonating element operating at a first band and has a first opening. The antenna structure also includes a third metal layer disposed over the second metal layer. The third metal layer forms a second antenna resonating element operating at a second band, which is different from the first band. The antenna structure further includes a first transmission line extending from the first metal layer to the second metal layer and a second transmission line extending from the first metal layer through the first opening to the third metal layer.
    Type: Application
    Filed: August 29, 2023
    Publication date: March 14, 2024
    Inventors: Yen-Ju LIN, Chung-Hsin CHIANG, Wun-Jian LIN, Shih-Huang YEH
  • Method for transferring signals via transmission interface and communications apparatus utilizing the same
    Patent number: 11929767
    Abstract: A transmission interface between at least a first module and a second module is proposed. The transmission interface includes at least two physical transmission mediums. Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated. The at least two physical transmission mediums include a first physical transmission medium arranged to carry a first multiplexed signal including a first IF signal and a reference clock signal. The first IF signal and the reference clock signal are at different frequencies.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: March 12, 2024
    Assignee: MEDIATEK INC.
    Inventors: Chieh-Hsun Hsiao, Ming-Chou Wu, Wen-Chang Lee, Narayanan Baskaran, Wei-Hsin Tseng, Jenwei Ko, Po-Sen Tseng, Hsin-Hung Chen, Chih-Yuan Lin, Caiyi Wang
  • Keyboard button with a thin sheet spring design
    Patent number: 11929216
    Abstract: A button mechanism includes a button, a module, and a thin sheet spring. The thin sheet spring is in physical communication with the button and with the module. The thin sheet spring exerts a tension force on the button and the module to bias the button toward a normal position. In response to a force greater than the tension force being exerted on the button, a portion of the thin sheet stretches to enable the button to be placed in a contact position. In response to the force being removed from the button, the tension force causes the thin sheet to snap back to an original position and biases the button toward the normal position.
    Type: Grant
    Filed: October 14, 2022
    Date of Patent: March 12, 2024
    Assignee: Dell Products L.P.
    Inventors: Minghao Hsieh, Chia-Chen Lin, Jer-Yo Lee, Po-Fei Tsai, Chang-Hsin Chen
  • Memory device having a negative voltage circuit
    Patent number: 11929116
    Abstract: A memory device and a method for operating the memory device are provided. The memory device includes a memory cell and a bit line connected to the memory cell. A negative voltage generator is connected to the bit line. The negative voltage generator, when enabled, is operative to provide a first write path for the bit line. A control circuit is connected to the negative voltage generator and the bit line. The control circuit is operative to provide a second write path for the bit line when the negative voltage generator is not enabled.
    Type: Grant
    Filed: January 23, 2023
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hsin Nien, Hidehiro Fujiwara, Chih-Yu Lin, Yen-Huei Chen
  • Dielectric grating apparatus
    Patent number: 11927780
    Abstract: A dielectric grating apparatus comprises a substrate; a grating layer, disposed above the substrate; a first interference layer, disposed above the substrate; and a second interference layer, adjacent to the first interference layer, wherein a refractive index of a material of the second interference layer is greater than a refractive index of a material of the first interference layer.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: March 12, 2024
    Assignee: NATIONAL CHUNG SHAN INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Jian-Hung Lin, Chiang-Hsin Lin, Po-Tse Tai, Tsong-Dong Wang, Bo-Kai Feng
  • OPTIMIZED CELL TRANSPLANT, AND PREPARATION METHOD AND USE THEREOF
    Publication number: 20240075071
    Abstract: Disclosed in the present invention is an optimized cell transplant. The optimized cell transplant is formed by performing gene induction and modification on a mesenchymal stem cell in the form of a small molecule and protein composition. The expression levels of CD200 gene, Galectin-9 gene and VISTA gene can be increased synchronously after cell culture. Vector virus infection and plasmid transfection are not required in the cell preparation process, so that high biological safety and great clinical application value of cells are achieved.
    Type: Application
    Filed: November 23, 2022
    Publication date: March 7, 2024
    Inventors: Ruei-Yue Liang, Kai-Ling Zhang, Ming-Hsi Chuang, Po-Cheng Lin, Peggy Leh Jiunn Wong, Chia-Hsin Lee
  • PHOTO DETECTOR
    Publication number: 20240080537
    Abstract: A photo detector including a photo sensor part and a power source module is provided. The power source module is fixed on the photo sensor part and electrically connected to the photo sensor part. The power source module is detachable and includes a handle.
    Type: Application
    Filed: August 8, 2023
    Publication date: March 7, 2024
    Applicant: InnoCare Optoelectronics Corporation
    Inventors: Sung-Pao Cheng, Hsin-Lin Lo
  • PLASMA DEVICE FOR SKIN REPAIR
    Publication number: 20240075308
    Abstract: The present invention provides a plasma device for skin repair, which includes a plasma head, a power supply, a gas supply source, and a control box. The plasma head includes an inner sleeve and an outer sleeve which are sleeved together. The inner sleeve has a first bottom portion having several first through holes. The outer sleeve has a second bottom portion having several second through holes. A gap is formed between the first bottom portion and the second bottom portion. The power supply is configured to provide 13.56 MHz to 54 MHz radio frequency power to generate a discharge in the gap. The gas supply source is configured to provide reaction gas into the gap, and plasma is formed by the reaction gas under the discharge. The control box is configured to control operating parameters of the plasma head, the power supply, and the gas supply source.
    Type: Application
    Filed: August 28, 2023
    Publication date: March 7, 2024
    Applicant: Longyi Bio-Medical Technology Ltd.
    Inventors: Che-hsin LIN, Yao-hsien WANG
  • Self-powered sensing and transmitting device
    Patent number: 11919336
    Abstract: A self-powered sensing and transmitting device is provided and includes a piezoelectric generator, a carrying structure stacked with the piezoelectric generator, an encapsulation support structure including an encapsulation portion encapsulating the piezoelectric generator and the carrying structure and two supporting portions connected to two ends of the encapsulation portion, and a fixed support structure for being correspondingly coupled with the two supporting portions and fixed on a flexible surface. The self-powered sensing and transmitting device can be applied to a tire monitoring system and a motion monitoring system.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: March 5, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chia-Hsin Lin, Min-Yan Dong
  • Integrated circuit, system and method of forming the same
    Patent number: 11923369
    Abstract: An integrated circuit includes a set of power rails on a back-side of a substrate, a first flip-flop, a second flip-flop and a third flip-flop. The set of power rails extend in a first direction. The first flip-flop includes a first set of conductive structures extending in the first direction. The second flip-flop abuts the first flip-flop at a first boundary, and includes a second set of conductive structures extending in the first direction. The third flip-flop abuts the second flip-flop at a second boundary, and includes a third set of conductive structures extending in the first direction. The first, second and third flip-flop are on a first metal layer and are on a front-side of the substrate opposite from the back-side. The second set of conductive structures are offset from the first boundary and the second boundary in a second direction.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Hsin Chiu, Wei-Cheng Lin, Wei-An Lai, Jiann-Tyng Tzeng
  • Semiconductor structure having air gaps and method for manufacturing the same
    Patent number: 11923306
    Abstract: A method for manufacturing a semiconductor structure includes forming a plurality of dummy structures spaced apart from each other, forming a plurality of dielectric spacers laterally covering the dummy structures to form a plurality of trenches defined by the dielectric spacers, filling a conductive material into the trenches to form electrically conductive features, selectively depositing a capping material on the electrically conductive features to form a capping layer, removing the dummy structures to form a plurality of recesses defined by the dielectric spacers, filling a sacrificial material into the recesses so as to form sacrificial features, depositing a sustaining layer on the sacrificial features, and removing the sacrificial features to form air gaps confined by the sustaining layer and the dielectric spacers.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Wei Su, Chia-Tien Wu, Hsin-Ping Chen, Shau-Lin Shue
  • Semiconductor device
    Patent number: 11923427
    Abstract: A semiconductor device includes a semiconductor substrate, a control gate, a select gate, a charge trapping structure, and a dielectric structure. The semiconductor substrate has a drain region, a source region, and a channel region between the drain region and the source region. The control gate is over the channel region of the semiconductor substrate. The select gate is over the channel region of the semiconductor substrate and separated from the control gate. The charge trapping structure is between the control gate and the semiconductor substrate. The dielectric structure is between the select gate and the semiconductor substrate. The dielectric structure has a first part and a second part, the first part is between the charge trapping structure and the second part, and the second part is thicker than the first part.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Wei-Cheng Wu, Te-Hsin Chiu
  • Semiconductor structure having air gaps and method for manufacturing the same
    Patent number: 11923243
    Abstract: A method for manufacturing a semiconductor structure includes preparing a dielectric structure formed with trenches respectively defined by lateral surfaces of the dielectric structure, forming spacer layers on the lateral surfaces, filling an electrically conductive material into the trenches to form electrically conductive features, selectively depositing a blocking layer on the dielectric structure, selectively depositing a dielectric material on the electrically conductive features to form a capping layer, removing the blocking layer and the dielectric structure to form recesses, forming sacrificial features in the recesses, forming a sustaining layer to cover the sacrificial features; and removing the sacrificial features to obtain the semiconductor structure formed with air gaps confined by the sustaining layer and the spacer layers.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Yen Huang, Ting-Ya Lo, Shao-Kuan Lee, Chi-Lin Teng, Cheng-Chin Lee, Shau-Lin Shue, Hsiao-Kang Chang