Patents by Inventor Hsin-An Lin

Hsin-An Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240121939
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a word line, a first capacitor, a second capacitor, a first bit line and a second bit line. The word line is disposed on the substrate and extends along a first direction. The first capacitor extends along a second direction different from the first direction and is located at a first level. The second capacitor extends along the second direction and is located at a second level different from the first level. The first bit line is electrically connected to the first capacitor and the word line. The second bit line is electrically connected to the second capacitor and the word line.
    Type: Application
    Filed: October 11, 2022
    Publication date: April 11, 2024
    Inventors: SHIH-FAN KUAN, HSU-CHENG FAN, JIANN-JONG WANG, CHUNG-HSIN LIN, YU-TING LIN
  • Publication number: 20240121685
    Abstract: A method of reducing gray energy consumption and achieving optimal gray energy saving for carbon neutralization is proposed. In a cellular network, each cell or BS (group of cells) has renewable (green) and non-renewable (gray, on-grid power) energy sources. The renewable (green) energy is highly variable and unpredictable, while non-renewable (gray, on-grid power) is stable but is not renewable and thus has more carbon impact. Each cell or BS (group of cells) services is associated UEs when it is on. In one novel aspect, a cell or BS (group of cells) that consumes more non-renewable energy can give some or all of its served UEs to another cell or BS (group of cells) that consumes less non-renewable energy.
    Type: Application
    Filed: September 21, 2023
    Publication date: April 11, 2024
    Inventors: Chien-Sheng Yang, I-Kang Fu, YUAN-CHIEH LIN, Chia-Lin Lai, Yu-Hsin Lin, Yun-Hsuan Chang
  • Publication number: 20240121940
    Abstract: A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a substrate, a word line, a first capacitor, a second capacitor, a first bit line and a second bit line. The word line is disposed on the substrate and extends along a first direction. The first capacitor extends along a second direction different from the first direction and is located at a first level. The second capacitor extends along the second direction and is located at a second level different from the first level. The first bit line is electrically connected to the first capacitor and the word line. The second bit line is electrically connected to the second capacitor and the word line.
    Type: Application
    Filed: July 13, 2023
    Publication date: April 11, 2024
    Inventors: SHIH-FAN KUAN, HSU-CHENG FAN, JIANN-JONG WANG, CHUNG-HSIN LIN, YU-TING LIN
  • Publication number: 20240121718
    Abstract: Some of the present implementations provide a method for a user equipment (UE) for receiving a power saving signal. The method receives, from a base station, a power saving signal comprising a minimum applicable K0 (K0min) that indicates a minimum scheduling offset restriction between a physical downlink control channel (PDCCH) and a physical downlink shared channel (PDSCH). The method determines an application delay based on a predefined value. The method then applies the minimum scheduling offset restriction after the application delay.
    Type: Application
    Filed: October 23, 2023
    Publication date: April 11, 2024
    Inventors: Yu-Hsin Cheng, Chie-Ming Chou, Wan-Chen Lin, Tsung-Hua Tsai
  • Publication number: 20240121995
    Abstract: Embodiments described herein relate to a sub-pixel. The sub-pixel includes an anode, overhang structures, separation structures, an organic light emitting diode (OLED) material, and a cathode. The anode is defined by adjacent first pixel isolation structures (PIS) and adjacent second PIS. The overhang structures are disposed on the first PIS. The overhang structures include a second structure disposed over the first structure and an intermediate structure disposed between the second structure and the first structure. A bottom surface of the second structure extends laterally past an upper surface of the first structure. The first structure is disposed over the first PIS. Separation structures are disposed over the second PIS. The OLED material is disposed over the anode and an upper surface of the separation structures. The cathode disposed over the OLED material and an upper surface of the separation structures.
    Type: Application
    Filed: December 19, 2023
    Publication date: April 11, 2024
    Inventors: Jungmin LEE, Chung-chia CHEN, Ji Young CHOUNG, Yu-hsin LIN
  • Patent number: 11955317
    Abstract: A radio frequency (RF) match assembly for a chemical vapor deposition processing chamber. The assembly includes a top electrically insulating column and a bottom electrically insulating column. The assembly further includes a one-piece RF match strap that has a head, a main body and a body extension. The main body of the one-piece RF match strap is configured to extend through the top electrically insulating column and the bottom electrically insulating column. A flexible chamber lid strap connects the processing chamber to the top of the one piece RF match strap.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Sze Chen, Yu Li Wang, Yin-Tun Chou, Yuan-Hsin Chi, Sheng-Yuan Lin
  • Patent number: 11955634
    Abstract: A particle structure of cathode material and a preparation method thereof is provided. Firstly, a precursor for forming a core is provided. The precursor includes at least nickel, cobalt and manganese. Secondly, a metal salt and a lithium ion compound are provided. The metal salt includes at least potassium, aluminum and sulfur. After that, the metal salt, the lithium ion compound and the precursor are mixed, and a mixture is formed. Finally, the mixture is subjected to a heat treatment step, and a cathode material particle structure is formed to include the core, a first coating layer coated on the core and a second coating layer coated on the first coating layer. The core includes potassium, aluminum and a Li-M-O based material. The first coating layer includes potassium and aluminum, and a potassium content of the first coating layer is higher than a potassium content of the core. The second coating layer includes sulfur.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: April 9, 2024
    Assignee: ADVANCED LITHIUM ELECTROCHEMISTRY CO., LTD.
    Inventors: Ching-Hao Yu, Nae-Lih Wu, Chia-Hsin Lin
  • Patent number: 11951901
    Abstract: A display system suitable for a vehicle is provided. The display system suitable for the vehicle includes a center console, a processing device, and a display device. The center console is configured to generate a power sequence according to a customization setting, and the power sequence corresponds to content of a data table. The processing device is configured to receive the power sequence and decodes the power sequence through a lookup table to generate a decoding result. The lookup table includes the content of the data table. The display device is coupled to the processing device and is configured to display a display image according to the decoding result.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: April 9, 2024
    Assignee: Coretronic Corporation
    Inventors: Jui-Ta Liu, Wen-Chang Chien, Tsung-Hsin Yeh, Shao-Chi Lin
  • Patent number: 11952676
    Abstract: A silicon carbide crystal includes a seed layer, a bulk layer and a stress buffering structure formed between the seed layer and the bulk layer. The seed layer, the bulk layer and the stress buffering structure are each formed with a dopant that cycles between high and low dopant concentration. The stress buffering structure includes a plurality of stacked buffer layers and a transition layer over the buffer layers. The buffer layer closest to the seed layer has the same variation trend of the dopant concentration as the buffer layer closest to the transition layer, and the dopant concentration of the transition layer is equal to the dopant concentration of the seed layer.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: April 9, 2024
    Assignee: GLOBALWAFERS CO., LTD.
    Inventors: Ching-Shan Lin, Jian-Hsin Lu, Chien-Cheng Liou, Man-Hsuan Lin
  • Publication number: 20240114727
    Abstract: Embodiments described herein relate to a sub-pixel. The sub-pixel includes an anode, overhang structures, separation structures, an organic light emitting diode (OLED) material, and a cathode. The anode is defined by adjacent first pixel isolation structures (PIS) and adjacent second PIS. The overhang structures are disposed on the first PIS. The overhang structures include a second structure disposed over the first structure and an intermediate structure disposed between the second structure and the first structure. A bottom surface of the second structure extends laterally past an upper surface of the first structure. The first structure is disposed over the first PIS. Separation structures are disposed over the second PIS. The OLED material is disposed over the anode and an upper surface of the separation structures. The cathode disposed over the OLED material and an upper surface of the separation structures.
    Type: Application
    Filed: December 5, 2023
    Publication date: April 4, 2024
    Inventors: Jungmin LEE, Chung-chia CHEN, Ji Young CHOUNG, Yu-hsin LIN
  • Publication number: 20240111453
    Abstract: A memory device and a management method thereof are provided. The memory device includes a controller and at least one memory channel. The memory channel includes at least one memory chip. The at least one memory chip is commonly coupled to the controller through an interrupt signal wire. The at least one memory chip generates at least one local interrupt signal and performs a logic operation on the at least one local interrupt signal to generate a common interrupt signal. The interrupt signal wire is configured to transmit the common interrupt signal to the controller.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Jia-Xing Lin, Nai-Ping Kuo, Shih-Chou Juan, Chien-Hsin Liu, Shunli Cheng
  • Publication number: 20240113262
    Abstract: A light-emitting device includes: a semiconductor stack, including a first semiconductor layer, an active region and a second semiconductor layer; a first contact electrode and a second contact electrode formed on the semiconductor stack, wherein the first contact electrode includes a first contact part formed on the first semiconductor layer and the second contact electrode includes a second contact part formed on the second semiconductor layer; an insulating stack formed on the semiconductor stack, including an opening on the second contact part; a first electrode pad and a second electrode pad formed on the insulating stack, wherein the second electrode pad filled in the opening and connecting the second contact part; wherein the second electrode pad includes an upper surface, and the upper surface includes a platform area and a depression area on the second contact part; wherein the platform area has a maximum height relative to other areas of the upper surface; wherein an area of a projection of the plat
    Type: Application
    Filed: September 1, 2023
    Publication date: April 4, 2024
    Inventors: Hsin-Ying WANG, Hui-Chun YEH, Jhih-Yong YANG, Chen OU, Cheng-Lin LU
  • Publication number: 20240113188
    Abstract: An integrated circuit (IC) structure includes a semiconductor substrate, a first gate line, a second gate line, and a first auxiliary gate portion. The semiconductor substrate comprises a semiconductor fin. The semiconductor fin extends substantially along a first direction. The first gate line and the second gate line extend substantially along a second direction different form the first direction from a top view. The first auxiliary gate portion connects the first gate line to the second gate line from the top view.
    Type: Application
    Filed: March 27, 2023
    Publication date: April 4, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Li CHIU, Yi-Juei LEE, Yu-Jie YE, Chi-Hsin CHANG, Chun-Jun LIN
  • Publication number: 20240114591
    Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. The UE sends a request message to a core network. The request message requests joining one or more requested multicast broadcast service (MBS) sessions. The UE receives a response message from the core network. The response message contains received MBS information indicating one or more admitted MBS sessions. The received MBS information includes a respective IP address type (IPAT) field. The IPAT field indicates a type of an IP address corresponding to each of the one or more admitted MBS sessions. The UE decodes the IP address corresponding to each of the one or more admitted MBS sessions according to the type indicated by the respective IPAT field.
    Type: Application
    Filed: September 22, 2023
    Publication date: April 4, 2024
    Inventors: Yu-Hsin Lin, Shao-Liang Yeh, Yuan-Chieh Lin
  • Patent number: 11948834
    Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a semiconductor substrate, a first ILD layer over the semiconductor substrate, and a first metal feature in the first ILD layer; depositing a second metal feature over the workpiece such that the second metal feature is electrically coupled to the first metal feature; patterning the second metal feature to form a first trench adjacent to the first metal feature; depositing a blocking layer over the workpiece, wherein the blocking layer selectively attaches to the first ILD layer; depositing a barrier layer over the workpiece, wherein the barrier layer selectively forms over the second metal feature relative to the first ILD layer; and depositing a second ILD layer over the workpiece.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yen Huang, Hai-Ching Chen, Shau-Lin Shue
  • Patent number: 11950413
    Abstract: An integrated circuit device includes a plurality of metal gates each having a metal electrode and a high-? dielectric and a plurality of polysilicon gates each having a polysilicon electrode and conventional (non high-?) dielectrics. The polysilicon gates may have adaptations for operation as high voltage gates including thick dielectric layers and area greater than one ?m2. Polysilicon gates with these adaptations may be operative with gate voltages of 10 V or higher and may be used in embedded memory devices.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Han Lin, Te-Hsin Chiu
  • Patent number: 11947251
    Abstract: An illumination system provides an illumination beam and includes a red light source, a green light source, a blue light source, a first supplementary light source, a first X-shaped light-splitting assembly, a first light-splitting element, and a light-uniforming element. The red light source provides a red beam. The green light source provides a green beam. The blue light source provides a blue beam. The first supplementary light source provides a first supplementary beam. The first X-shaped light-splitting assembly guides the first supplementary beam and the blue beam to the first light-splitting element. The first light-splitting element guides the red beam, the green beam, the blue beam, and the first supplementary beam to the light-uniforming element. The first supplementary beam is a red supplementary beam or a blue supplementary beam, and the illumination system includes at least five light-emitting elements. A projection apparatus including the above illumination system is also provided.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: April 2, 2024
    Assignee: Coretronic Corporation
    Inventors: Chi-Fu Liu, Tsung-Hsin Liao, Chun-Li Chen, Hung-Yu Lin
  • Publication number: 20240107819
    Abstract: Embodiments described herein relate to a sub-pixel. The sub-pixel includes an anode, overhang structures, separation structures, an organic light emitting diode (OLED) material, and a cathode. The anode is defined by adjacent first pixel isolation structures (PIS) and adjacent second PIS. The overhang structures are disposed on the first PIS. The overhang structures include a second structure disposed over the first structure and an intermediate structure disposed between the second structure and the first structure. A bottom surface of the second structure extends laterally past an upper surface of the first structure. The first structure is disposed over the first PIS. Separation structures are disposed over the second PIS. The OLED material is disposed over the anode and an upper surface of the separation structures. The cathode disposed over the OLED material and an upper surface of the separation structures.
    Type: Application
    Filed: December 5, 2023
    Publication date: March 28, 2024
    Inventors: Jungmin LEE, Chung-chia CHEN, Ji Young CHOUNG, Yu-hsin LIN
  • Publication number: 20240105480
    Abstract: A wafer storage elevator and method for detecting wafer position shift. The elevator includes a first storage elevator sidewall, a second storage elevator sidewall, and a storage seat positioned between the first and second storage elevator sidewalls. A first mirror block is coupled to a front side of the storage seat having a mirror positioned on a top surface of the block, and a second mirror block is coupled to the front side of the storage seat having a mirror that is positioned on the top surface of the second mirror block. The mirror of the first mirror block reflects a laser beam from an emission sensor to the second mirror block, and the mirror of the second mirror block reflects the laser beam from the mirror of the first mirror block to a receive sensor. A wafer misalignment is determined based upon an output of the receive sensor.
    Type: Application
    Filed: January 4, 2023
    Publication date: March 28, 2024
    Inventors: Ming-Sze Chen, Yuan-Hsin Chi, Hung-Chih Wang, Sheng-Yuan Lin
  • Publication number: 20240101784
    Abstract: A novel additive for recycling thermoset materials, its related recyclable thermoset composition and its application are disclosed. Specifically, the composition of the additive comprises at least one copolymer that has at least one carbamate group, at least one carbonate group and/or at least one urea group, and a number-average molecular weight of the copolymer is between 100 and 50,000 Da.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 28, 2024
    Inventors: Chien-Hsin Wu, Ying-Chi Huang, Ying-Feng Lin, Wen-Chang Chen, Ho-Ching Huang, Ru-Jong Jeng