Patents by Inventor Hsin-Che Chiang
Hsin-Che Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200044073Abstract: The present disclosure describes structure and method of a fin field-effect transistor (finFET) device. The finFET device includes: a substrate, a fin over the substrate, and a gate structure over the fin. The gate structure includes a work-function metal (WFM) layer over an inner sidewall of the gate structure. A topmost surface of the WFM layer is lower than a top surface of the gate structure. The gate structure also includes a filler gate metal layer over the topmost surface of the WFM layer. A top surface of the filler gate metal layer is substantially co-planar with the top surface of the gate structure. The gate structure further includes a self-assembled monolayer (SAM) between the filler gate metal layer and the WFM layer.Type: ApplicationFiled: February 27, 2019Publication date: February 6, 2020Applicant: Taiwam Semiconductor Manufacturing Co., Ltd.Inventors: Ju-Li HUANG, Chun-Sheng Liang, Ming-Hsi Yeh, Ying-Liang Chuang, Hsin-Che Chiang, Chun-Ming Yang, Yu-Chi Pan
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Patent number: 10541317Abstract: Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer.Type: GrantFiled: March 1, 2018Date of Patent: January 21, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ju-Li Huang, Chun-Sheng Liang, Ming-Chi Huang, Ming-Hsi Yeh, Ying-Liang Chuang, Hsin-Che Chiang
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Patent number: 10535653Abstract: A semiconductor structure includes a pair of gate structures and an isolation structure. Each of the gate structures includes a work function metal, a gate, and a barrier layer between the work function metal and the gate. The isolation structure is disposed between the gate structures. The barrier layer covers a sidewall of the isolation structure.Type: GrantFiled: December 17, 2017Date of Patent: January 14, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Jen Chen, Chun-Sheng Liang, Shu-Hui Wang, Shih-Hsun Chang, Hsin-Che Chiang
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Patent number: 10529629Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.Type: GrantFiled: April 30, 2018Date of Patent: January 7, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ju-Li Huang, Hsin-Che Chiang, Ju-Yuan Tzeng, Wei-Ze Xu, Yueh-Yi Chen, Shu-Hui Wang, Shih-Hsun Chang
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Publication number: 20190393326Abstract: A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer is formed over the high-k dielectric layer. The dummy metal layer includes fluorine. A high temperature process is performed to drive the fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer. Thereafter, the dummy metal layer is removed. At least one work function layer over the passivated high-k dielectric layer is formed. A fill metal layer is formed over the at least one work function layer.Type: ApplicationFiled: August 30, 2019Publication date: December 26, 2019Inventors: Hsin-Che CHIANG, Ju-Yuan TZENG, Chun-Sheng LIANG, Shu-Hui WANG, Kuo-Hua PAN
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Publication number: 20190385896Abstract: In one exemplary aspect, a method for semiconductor manufacturing comprises forming first and second silicon nitride features on sidewall surfaces of a contact hole, where the contact hole is disposed in a dielectric layer and above a source/drain (S/D) feature. The method further comprises forming a contact plug in the contact hole, the contact plug being electrically coupled to the S/D feature, removing a top portion of the contact plug to create a recess in the contact hole, forming a hard mask layer in the recess, and removing the first and second silicon nitride features via selective etching to form first and second air gaps, respectively.Type: ApplicationFiled: June 15, 2018Publication date: December 19, 2019Inventors: Hsin-Che Chiang, Ju-Li Huang, Chun-Sheng Liang, Jeng-Ya David Yeh
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Patent number: 10475895Abstract: A semiconductor device includes a substrate, a first dielectric layer, a first device and a second device. The first dielectric layer is disposed on the substrate. The first device is disposed on the first dielectric layer on a first region of the substrate, and includes two first spacers, a second dielectric layer and a first gate structure. The first spacers are separated to form a first trench. The second dielectric layer is disposed on side surfaces and a bottom surface of the first trench. The first gate structure is disposed on the second dielectric layer. The second device is disposed on a second region of the substrate, and includes two second spacers and a second gate structure. The second spacers are disposed on the first dielectric layer and are separated to form a second trench. The second gate structure is disposed on the substrate within the second trench.Type: GrantFiled: June 21, 2017Date of Patent: November 12, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Che Chiang, Ju-Yuan Tzeng, Chun-Sheng Liang, Shu-Hui Wang, Chih-Yang Yeh, Jeng-ya David Yeh
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Publication number: 20190333826Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.Type: ApplicationFiled: April 30, 2018Publication date: October 31, 2019Inventors: Ju-Li Huang, Hsin-Che Chiang, Ju-Yuan Tzeng, Wei-Ze Xu, Yueh-Yi Chen, Shu-Hui Wang, Shih-Hsun Chang
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Publication number: 20190273149Abstract: Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer.Type: ApplicationFiled: March 1, 2018Publication date: September 5, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ju-Li HUANG, Chun-Sheng LIANG, Ming-Chi HUANG, Ming-Hsi YEH, Ying-Liang CHUANG, Hsin-Che CHIANG
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Patent number: 10403737Abstract: A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer is formed over the high-k dielectric layer. The dummy metal layer includes fluorine. A high temperature process is performed to drive the fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer. Thereafter, the dummy metal layer is removed. At least one work function layer over the passivated high-k dielectric layer is formed. A fill metal layer is formed over the at least one work function layer.Type: GrantFiled: November 16, 2018Date of Patent: September 3, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Che Chiang, Ju-Yuan Tzeng, Chun-Sheng Liang, Shu-Hui Wang, Kuo-Hua Pan
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Publication number: 20190165117Abstract: A semiconductor device includes a substrate, a gate stack. The substrate includes a semiconductor fin. The gate stack is disposed on the semiconductor fin. The gate stack includes a dielectric layer disposed over the semiconductor fin, and a metal stack disposed over the dielectric layer and having a first metallic layer and a second metallic layer over the first metallic layer, and a gate electrode disposed over the metal stack. The first metallic layer and the second metallic layer have a first element, and a percentage of the first element in the first metallic layer is greater than that in the second metallic layer.Type: ApplicationFiled: August 28, 2018Publication date: May 30, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Che CHIANG, Ju-Yuan TZENG, Chun-Sheng LIANG, Chih-Yang YEH, Shu-Hui WANG, Jeng-Ya David YEH
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Publication number: 20190088763Abstract: A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer is formed over the high-k dielectric layer. The dummy metal layer includes fluorine. A high temperature process is performed to drive the fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer. Thereafter, the dummy metal layer is removed. At least one work function layer over the passivated high-k dielectric layer is formed. A fill metal layer is formed over the at least one work function layer.Type: ApplicationFiled: November 16, 2018Publication date: March 21, 2019Inventors: Hsin-Che CHIANG, Ju-Yuan TSENG, Chun-Sheng LIANG, Shu-Hui WANG, Kuo-Hua PAN
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Patent number: 10164065Abstract: In a method for manufacturing a semiconductor device, a first raised structure is formed on a surface of a substrate. The first raised structure includes a top surface and a side surface adjoining the top surface. The side surface includes an upper portion, a middle portion, and a lower portion. A deposition operation is performed with a precursor to form a first film on the top surface, the upper portion and the lower portion of the side surface, and the surface of the substrate. Performing the deposition operation includes controlling a saturated vapor pressure of the precursor. A re-deposition operation is performed on the first film and the first raised structure, so as to form a film structure. A thickness of the film structure on the middle portion of the side surface is smaller than a thickness of the film structure on the top surface.Type: GrantFiled: June 22, 2017Date of Patent: December 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Che Chiang, Ju-Yuan Tzeng, Chun-Sheng Liang, Shu-Hui Wang, Chih-Yang Yeh, Jeng-Ya David Yeh
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Publication number: 20180350956Abstract: In a method for manufacturing a semiconductor device, a first raised structure is formed on a surface of a substrate. The first raised structure includes a top surface and a side surface adjoining the top surface. The side surface includes an upper portion, a middle portion, and a lower portion. A deposition operation is performed with a precursor to form a first film on the top surface, the upper portion and the lower portion of the side surface, and the surface of the substrate. Performing the deposition operation includes controlling a saturated vapor pressure of the precursor. A re-deposition operation is performed on the first film and the first raised structure, so as to form a film structure. A thickness of the film structure on the middle portion of the side surface is smaller than a thickness of the film structure on the top surface.Type: ApplicationFiled: June 22, 2017Publication date: December 6, 2018Inventors: Hsin-Che CHIANG, Ju-Yuan TZENG, Chun-Sheng LIANG, Shu-Hui WANG, Chih-Yang YEH, Jeng-Ya David YEH
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Publication number: 20180342595Abstract: A semiconductor device includes a substrate, a first dielectric layer, a first device and a second device. The first dielectric layer is disposed on the substrate. The first device is disposed on the first dielectric layer on a first region of the substrate, and includes two first spacers, a second dielectric layer and a first gate structure. The first spacers are separated to form a first trench. The second dielectric layer is disposed on side surfaces and a bottom surface of the first trench. The first gate structure is disposed on the second dielectric layer. The second device is disposed on a second region of the substrate, and includes two second spacers and a second gate structure. The second spacers are disposed on the first dielectric layer and are separated to form a second trench. The second gate structure is disposed on the substrate within the second trench.Type: ApplicationFiled: June 21, 2017Publication date: November 29, 2018Inventors: Hsin-Che CHIANG, Ju-Yuan TZENG, Chun-Sheng LIANG, Shu-Hui WANG, Chih-Yang YEH, Jeng-Ya David YEH
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Patent number: 10134873Abstract: A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer is formed over the high-k dielectric layer. The dummy metal layer includes fluorine. A high temperature process is performed to drive the fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer. Thereafter, the dummy metal layer is removed. At least one work function layer over the passivated high-k dielectric layer is formed. A fill metal layer is formed over the at least one work function layer.Type: GrantFiled: November 18, 2016Date of Patent: November 20, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Che Chiang, Ju-Yuan Tzeng, Chun-Sheng Liang, Shu-Hui Wang, Kuo-Hua Pan
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Patent number: 10128156Abstract: A FinFET device and a method for fabricating the same are provided. In the method for fabricating the FinFET device, at first, a semiconductor substrate having fin structures is provided. Then, a dielectric layer and a dummy gate structure are sequentially formed on the semiconductor substrate. The dummy gate structure includes two dummy gate stacks, a gate isolation structure formed between and adjoining the dummy gate stacks, and two spacers sandwiching the dummy gate stacks and the gate isolation structure. Then, the dummy gate stacks are removed to expose portions of the dielectric layer and to expose sidewalls of portions of the spacers. Thereafter, an oxidizing treatment is conducted on the exposed portions of the dielectric layer and the portions of the spacers to increase quality of the dielectric layer.Type: GrantFiled: November 29, 2017Date of Patent: November 13, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Che Chiang, Wen-Li Chiu, Chun-Sheng Liang, Jeng-Ya David Yeh
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Publication number: 20180145149Abstract: A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer is formed over the high-k dielectric layer. The dummy metal layer includes fluorine. A high temperature process is performed to drive the fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer. Thereafter, the dummy metal layer is removed. At least one work function layer over the passivated high-k dielectric layer is formed. A fill metal layer is formed over the at least one work function layer.Type: ApplicationFiled: November 18, 2016Publication date: May 24, 2018Inventors: Hsin-Che CHIANG, Ju-Yuan TZENG, Chun-Sheng LIANG, Shu-Hui WANG, Kuo-Hua PAN
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Publication number: 20180108653Abstract: A semiconductor structure includes a pair of gate structures and an isolation structure. Each of the gate structures includes a work function metal, a gate, and a barrier layer between the work function metal and the gate. The isolation structure is disposed between the gate structures. The barrier layer covers a sidewall of the isolation structure.Type: ApplicationFiled: December 17, 2017Publication date: April 19, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Jen CHEN, Chun-Sheng LIANG, Shu-Hui WANG, Shih-Hsun CHANG, Hsin-Che CHIANG
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Patent number: 9859273Abstract: A process of manufacturing a semiconductor structure is provided. The process begins with forming a work function metal layer on a substrate, and a hardmask is covered over the work function metal layer. A trench is formed to penetrate the hardmask and the work function metal layer, and an isolation structure is filled in the trench.Type: GrantFiled: May 28, 2015Date of Patent: January 2, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Jen Chen, Chun-Sheng Liang, Shu-Hui Wang, Shih-Hsun Chang, Hsin-Che Chiang