Patents by Inventor Hsin-Chieh Huang

Hsin-Chieh Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12237395
    Abstract: A high electron mobility transistor (HEMT) includes a substrate, a channel layer, a barrier layer and a passivation layer. A contact structure is disposed on the passivation layer and extends through the passivation layer and the barrier layer to directly contact the channel layer. The contact structure includes a metal layer, and the metal layer includes a metal material doped with a first additive. A weight percentage of the first additive in the metal layer is between 0% and 2%.
    Type: Grant
    Filed: February 20, 2022
    Date of Patent: February 25, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ko-Wei Lin, Chun-Chieh Chiu, Chun-Ling Lin, Shu Min Huang, Hsin-Fu Huang
  • Patent number: 12237380
    Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.
    Type: Grant
    Filed: July 17, 2023
    Date of Patent: February 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ming Chang, Chi-Wen Liu, Cheng-Chien Li, Hsin-Chieh Huang
  • Publication number: 20250063866
    Abstract: A display apparatus includes a driving backplane, a plurality of light emitting components, a first bank layer and a plurality of scattering particles. The first bank layer is disposed on the driving backplane. The first bank layer has a plurality of first openings and a plurality of oblique surfaces defining the first openings. The light emitting components respectively overlap with the first openings of the first bank layer. The scattering particles are disposed on a plurality of light emitting surfaces of the light emitting components. A plurality of air gaps exist between the scattering particles and the oblique surfaces of the first bank layer.
    Type: Application
    Filed: December 27, 2023
    Publication date: February 20, 2025
    Inventors: Chun-Chieh Li, Sheng-Ming Huang, Han-Sheng Nian, Yu-Cheng Shih, Hsin-Hung Li
  • Patent number: 12224209
    Abstract: A manufacturing method of a semiconductor device includes forming a stack of first semiconductor layers and second semiconductor layers alternatively formed on top of one another, where a topmost layer of the stack is one of the second semiconductor layers; forming a patterned mask layer on the topmost layer of the stack; forming a trench in the stack based on the patterned mask layer to form a fin structure; forming a cladding layer extending along sidewalls of the fin structure; and removing the patterned mask layer and a portion of the cladding layer by performing a two-step etching process, where the portion of the cladding layer is removed to form cladding spacers having a concave top surface with a recess depth increasing from the sidewalls of the fin structure.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: February 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chao, Hsin-Chieh Huang, Yu-Wen Wang
  • Publication number: 20250047201
    Abstract: A power converter is coupled between a power source and multiple loads, and the power converter includes a first switch module. The switch module includes an inductor, a first switch, a second switch, a third switch, and a fourth switch. The first switch, the second switch, the third switch, and the fourth switch are configured to be turned on or turned off so that the inductor is stored energy or released energy to converter the power source into multiple voltages to the multiple loads.
    Type: Application
    Filed: September 20, 2023
    Publication date: February 6, 2025
    Inventors: Hung-Chieh LIN, Yi-Ping HSIEH, Hsin-Chih CHEN, Hung-Yu HUANG
  • Patent number: 12205822
    Abstract: Implementations described herein provide a method of forming a semiconductor device. The method includes forming a nanostructure having a first set of layers of a first material and a second set of layers, alternating with the first set of layers, having a second material. The method further includes depositing a hard mask on a top layer of the first set of layers, the hard mask including a first hard mask layer on the top layer of the first set of layers and a second hard mask layer on the first hard mask layer. The method also includes depositing elements of a cladding structure on sidewalls of the nanostructure and the hard mask. The method further includes removing a top portion of the cladding structure. The method further includes removing the second hard mask layer after removing the top portion of the cladding structure.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: January 21, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chao, Hsin-Chieh Huang, Yu-Wen Wang
  • Publication number: 20240395858
    Abstract: A semiconductor device includes a first channel structure extending along a first lateral direction and a second channel structure extending along the first lateral direction. The second channel structure is spaced apart from the first channel structure. The semiconductor device further includes a high-k dielectric structure extending along the first lateral direction and disposed between the first and second channel structures. The high-k dielectric structure has a bottom surface that comprises a bottommost portion and at least a first plateau portion elevated from the bottommost portion.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Chieh Huang, Chia-Cheng Chao, Yu-Wen Wang
  • Publication number: 20240371649
    Abstract: A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Inventors: Che-Lun Chang, Pin-Chuan Su, Hsin-Chieh Huang, Ming-Yuan Wu, Tzu kai Lin, Yu-Wen Wang, Che-Yuan Hsu
  • Patent number: 12131911
    Abstract: A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: October 29, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Lun Chang, Pin-Chuan Su, Hsin-Chieh Huang, Ming-Yuan Wu, Tzu kai Lin, Yu-Wen Wang, Che-Yuan Hsu
  • Publication number: 20240266336
    Abstract: An embodiment is a structure including a first package including a first die, and a molding compound at least laterally encapsulating the first die, a second package bonded to the first package with a first set of conductive connectors, the second package comprising a second die, and an underfill between the first package and the second package and surrounding the first set of conductive connectors, the underfill having a first portion extending up along a sidewall of the second package, the first portion having a first sidewall, the first sidewall having a curved portion and a planar portion.
    Type: Application
    Filed: April 17, 2024
    Publication date: August 8, 2024
    Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
  • Patent number: 11990454
    Abstract: An embodiment is a structure including a first package including a first die, and a molding compound at least laterally encapsulating the first die, a second package bonded to the first package with a first set of conductive connectors, the second package comprising a second die, and an underfill between the first package and the second package and surrounding the first set of conductive connectors, the underfill having a first portion extending up along a sidewall of the second package, the first portion having a first sidewall, the first sidewall having a curved portion and a planar portion.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
  • Patent number: 11984342
    Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
  • Patent number: 11948881
    Abstract: A semiconductor structure includes a die, a molding surrounding the die, a first dielectric layer disposed over the die and the molding, and a second dielectric layer disposed between the first dielectric layer and the die, and between the first dielectric layer and the molding. A material content ratio in the first dielectric layer is substantially greater than that in the second dielectric layer. In some embodiments, the material content ratio substantially inversely affects a mechanical strength of the first dielectric layer and the second dielectric layer.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsi-Kuei Cheng, Chih-Kang Han, Ching-Fu Chang, Hsin-Chieh Huang
  • Patent number: 11901303
    Abstract: An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an antenna region. The insulating encapsulation encapsulates the integrated circuit. The redistribution circuit structure is disposed on the integrated circuit and the insulating encapsulation. The redistribution circuit structure is electrically connected to the integrated circuit, and the redistribution circuit structure includes a redistribution region and a dummy region including a plurality of dummy patterns embedded therein, wherein the antenna region includes an inductor and a wiring-free dielectric portion, and the wiring-free dielectric portion of the antenna region is between the inductor and the dummy region.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
  • Patent number: 11854993
    Abstract: An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an antenna region. The insulating encapsulation encapsulates the integrated circuit. The redistribution circuit structure is disposed on the integrated circuit and the insulating encapsulation. The redistribution circuit structure is electrically connected to the integrated circuit, and the redistribution circuit structure includes a redistribution region and a dummy region including a plurality of dummy patterns embedded therein, wherein the antenna region includes an inductor and a wiring-free dielectric portion, and the wiring-free dielectric portion of the antenna region is between the inductor and the dummy region.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
  • Publication number: 20230361181
    Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.
    Type: Application
    Filed: July 17, 2023
    Publication date: November 9, 2023
    Inventors: Chia-Ming Chang, Chi-Wen Liu, Cheng-Chien Li, Hsin-Chieh Huang
  • Publication number: 20230335426
    Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.
    Type: Application
    Filed: June 16, 2023
    Publication date: October 19, 2023
    Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
  • Publication number: 20230326798
    Abstract: A manufacturing method of a semiconductor device includes forming a stack of first semiconductor layers and second semiconductor layers alternatively formed on top of one another, where a topmost layer of the stack is one of the second semiconductor layers; forming a patterned mask layer on the topmost layer of the stack; forming a trench in the stack based on the patterned mask layer to form a fin structure; forming a cladding layer extending along sidewalls of the fin structure; and removing the patterned mask layer and a portion of the cladding layer by performing a two-step etching process, where the portion of the cladding layer is removed to form cladding spacers having a concave top surface with a recess depth increasing from the sidewalls of the fin structure.
    Type: Application
    Filed: April 8, 2022
    Publication date: October 12, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chao, Hsin-Chieh Huang, Yu-Wen Wang
  • Patent number: 11749724
    Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ming Chang, Chi-Wen Liu, Cheng-Chien Li, Hsin-Chieh Huang
  • Patent number: D984513
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: April 25, 2023
    Assignee: CHUN KUANG OPTICS CORP.
    Inventors: Hsin-Chieh Huang, Sheng-Jung Lin, Shun-Wen Teng