Patents by Inventor Hsin-Chieh Huang
Hsin-Chieh Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11968556Abstract: A network quality measurement method and system are provided. In the method, a movement path and a movement speed of a vehicle device are determined according to a size of a space and an endurance time of the vehicle device, and the vehicle device is controlled to move on the movement path at the movement speed. During a movement of the vehicle device, a network quality in the space is measured according to a measurement frequency to generate network quality data. Whether the network quality in the space is changed is determined according to the network quality data. Whether there is an obstacle around the vehicle device is detected. When it is determined that the network quality in the space is changed or the obstacle is detected around the vehicle device, at least one of the movement path, the movement speed, and the measurement frequency is adjusted.Type: GrantFiled: December 26, 2021Date of Patent: April 23, 2024Assignee: Industrial Technology Research InstituteInventors: Hui-Ping Kuo, Sheng-Chieh Huang, Hsin-Hui Hwang, Yi-Ming Wu, Man Ju Chien
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Publication number: 20240113010Abstract: A semiconductor device is disclosed herein. The semiconductor device includes a routing structure. The routing structure has an intermediate conductive routing layer. The intermediate conductive routing layer includes a first mesh conductive layer formed in a predetermined second region of the semiconductor device and a second mesh conductive layer formed in a predetermined first region of the semiconductor device. The first mesh conductive layer and the second mesh conductive layer are electrically isolated from each other. The intermediate conductive routing layer further includes multiple first conductive islands formed in the predetermined first region and multiple second conductive islands formed in the predetermined second region.Type: ApplicationFiled: September 20, 2023Publication date: April 4, 2024Inventors: Po-Hsien Huang, Yu-Huei Lee, Hsin-Hung Lin, Chun-Yuan Shih, Lien-Chieh Yu
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Patent number: 11948881Abstract: A semiconductor structure includes a die, a molding surrounding the die, a first dielectric layer disposed over the die and the molding, and a second dielectric layer disposed between the first dielectric layer and the die, and between the first dielectric layer and the molding. A material content ratio in the first dielectric layer is substantially greater than that in the second dielectric layer. In some embodiments, the material content ratio substantially inversely affects a mechanical strength of the first dielectric layer and the second dielectric layer.Type: GrantFiled: July 8, 2021Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hsi-Kuei Cheng, Chih-Kang Han, Ching-Fu Chang, Hsin-Chieh Huang
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Patent number: 11901303Abstract: An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an antenna region. The insulating encapsulation encapsulates the integrated circuit. The redistribution circuit structure is disposed on the integrated circuit and the insulating encapsulation. The redistribution circuit structure is electrically connected to the integrated circuit, and the redistribution circuit structure includes a redistribution region and a dummy region including a plurality of dummy patterns embedded therein, wherein the antenna region includes an inductor and a wiring-free dielectric portion, and the wiring-free dielectric portion of the antenna region is between the inductor and the dummy region.Type: GrantFiled: July 25, 2022Date of Patent: February 13, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
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Patent number: 11854993Abstract: An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an antenna region. The insulating encapsulation encapsulates the integrated circuit. The redistribution circuit structure is disposed on the integrated circuit and the insulating encapsulation. The redistribution circuit structure is electrically connected to the integrated circuit, and the redistribution circuit structure includes a redistribution region and a dummy region including a plurality of dummy patterns embedded therein, wherein the antenna region includes an inductor and a wiring-free dielectric portion, and the wiring-free dielectric portion of the antenna region is between the inductor and the dummy region.Type: GrantFiled: May 19, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
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Publication number: 20230361181Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.Type: ApplicationFiled: July 17, 2023Publication date: November 9, 2023Inventors: Chia-Ming Chang, Chi-Wen Liu, Cheng-Chien Li, Hsin-Chieh Huang
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Publication number: 20230335426Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.Type: ApplicationFiled: June 16, 2023Publication date: October 19, 2023Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
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Publication number: 20230326798Abstract: A manufacturing method of a semiconductor device includes forming a stack of first semiconductor layers and second semiconductor layers alternatively formed on top of one another, where a topmost layer of the stack is one of the second semiconductor layers; forming a patterned mask layer on the topmost layer of the stack; forming a trench in the stack based on the patterned mask layer to form a fin structure; forming a cladding layer extending along sidewalls of the fin structure; and removing the patterned mask layer and a portion of the cladding layer by performing a two-step etching process, where the portion of the cladding layer is removed to form cladding spacers having a concave top surface with a recess depth increasing from the sidewalls of the fin structure.Type: ApplicationFiled: April 8, 2022Publication date: October 12, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Cheng Chao, Hsin-Chieh Huang, Yu-Wen Wang
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Patent number: 11749724Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.Type: GrantFiled: May 25, 2021Date of Patent: September 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Ming Chang, Chi-Wen Liu, Cheng-Chien Li, Hsin-Chieh Huang
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Patent number: 11618728Abstract: An ether-bridged dication is provided with two monovalent cations bonded via a carbon chain having ether group(s). The ether-bridged dication, monovalent cations, and anions are contained together within an ionic liquid electrolyte which is applied to a charge storage device. The ether-bridged dication, the ionic liquid electrolyte, and the charge storage device have operational abilities at room temperatures or below, and a reachable working potential of 3.5 V.Type: GrantFiled: April 20, 2021Date of Patent: April 4, 2023Assignee: NATIONAL CHENG KUNG UNIVERSITYInventors: Hsisheng Teng, I-wen Sun, Hsin-Chieh Huang, Yung-Che Yen, Jui-Cheng Chang
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Patent number: 11616133Abstract: A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess.Type: GrantFiled: April 25, 2022Date of Patent: March 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Che-Lun Chang, Shiao-Shin Cheng, Ji-Yin Tsai, Yu-Lin Tsai, Hsin-Chieh Huang, Ming-Yuan Wu, Jiun-Ming Kuo, Ming-Jie Huang, Yu-Wen Wang, Che-Yuan Hsu
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Publication number: 20220406920Abstract: A method for fabricating a semiconductor device includes forming a fin structure that includes a plurality of semiconductor channel layers alternatively spaced apart from one another with a plurality of semiconductor sacrificial layers. The method further includes forming a semiconductor cladding layer extending along sidewalls of the fin structure. The method further includes patterning the semiconductor cladding layer to have a top surface with a highest point and a lowest point by performing at least one sequential combination of a first etching process and a second etching process. A vertical difference between the highest point and the lowest point is less than 3 nanometers.Type: ApplicationFiled: January 26, 2022Publication date: December 22, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Cheng Chao, Hsin-Chieh Huang, Yu-Wen Wang
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Publication number: 20220367200Abstract: A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.Type: ApplicationFiled: June 20, 2022Publication date: November 17, 2022Inventors: Che-Lun Chang, Pin-Chuan Su, Hsin-Chieh Huang, Ming-Yuan Wu, Tzu kai Lin, Yu-Wen Wang, Che-Yuan Hsu
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Publication number: 20220359407Abstract: An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an antenna region. The insulating encapsulation encapsulates the integrated circuit. The redistribution circuit structure is disposed on the integrated circuit and the insulating encapsulation. The redistribution circuit structure is electrically connected to the integrated circuit, and the redistribution circuit structure includes a redistribution region and a dummy region including a plurality of dummy patterns embedded therein, wherein the antenna region includes an inductor and a wiring-free dielectric portion, and the wiring-free dielectric portion of the antenna region is between the inductor and the dummy region.Type: ApplicationFiled: July 25, 2022Publication date: November 10, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
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Publication number: 20220344460Abstract: A semiconductor device includes a first channel structure extending along a first lateral direction and a second channel structure extending along the first lateral direction. The second channel structure is spaced apart from the first channel structure. The semiconductor device further includes a high-k dielectric structure extending along the first lateral direction and disposed between the first and second channel structures. The high-k dielectric structure has a bottom surface that comprises a bottommost portion and at least a first plateau portion elevated from the bottommost portion.Type: ApplicationFiled: October 1, 2021Publication date: October 27, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Chieh Huang, Chia-Cheng Chao, Yu-Wen Wang
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Publication number: 20220319859Abstract: Implementations described herein provide a method of forming a semiconductor device. The method includes forming a nanostructure having a first set of layers of a first material and a second set of layers, alternating with the first set of layers, having a second material. The method further includes depositing a hard mask on a top layer of the first set of layers, the hard mask including a first hard mask layer on the top layer of the first set of layers and a second hard mask layer on the first hard mask layer. The method also includes depositing elements of a cladding structure on sidewalls of the nanostructure and the hard mask. The method further includes removing a top portion of the cladding structure. The method further includes removing the second hard mask layer after removing the top portion of the cladding structure.Type: ApplicationFiled: October 6, 2021Publication date: October 6, 2022Inventors: Chia-Cheng CHAO, Hsin-Chieh HUANG, Yu-Wen WANG
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Publication number: 20220278050Abstract: An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an antenna region. The insulating encapsulation encapsulates the integrated circuit. The redistribution circuit structure is disposed on the integrated circuit and the insulating encapsulation. The redistribution circuit structure is electrically connected to the integrated circuit, and the redistribution circuit structure includes a redistribution region and a dummy region including a plurality of dummy patterns embedded therein, wherein the antenna region includes an inductor and a wiring-free dielectric portion, and the wiring-free dielectric portion of the antenna region is between the inductor and the dummy region.Type: ApplicationFiled: May 19, 2022Publication date: September 1, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
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Publication number: 20220262926Abstract: A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess.Type: ApplicationFiled: April 25, 2022Publication date: August 18, 2022Inventors: Che-Lun Chang, Shiao-Shin Cheng, Ji-Yin Tsai, Yu-Lin Tsai, Hsin-Chieh Huang, Ming-Yuan Wu, Jiun-Ming Kuo, Ming-Jie Huang, Yu-Wen Wang, Che-Yuan Hsu
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Patent number: D984512Type: GrantFiled: September 30, 2020Date of Patent: April 25, 2023Assignee: CHUN KUANG OPTICS CORP.Inventors: Hsin-Chieh Huang, Sheng-Jung Lin, Shun-Wen Teng
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Patent number: D984513Type: GrantFiled: September 30, 2020Date of Patent: April 25, 2023Assignee: CHUN KUANG OPTICS CORP.Inventors: Hsin-Chieh Huang, Sheng-Jung Lin, Shun-Wen Teng