Patents by Inventor Hsin-Chieh Huang

Hsin-Chieh Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190285978
    Abstract: A picture selection method of projection touch for a projection touch system is provided. The projection touch system includes an image projection module, a sensing module, an image recognition module including at least one camera module and a processing unit. The picture selection method includes: the sensing module sensing and transferring a first projection coordinate on the target picture at a first time point of a sensing action; the sensing module sensing and transferring a second projection coordinate on the target picture at a second time point of the sensing action; the processing unit selecting at least one to-be-selected picture in the target picture based on the first and second projection coordinates and generating a set of selected image data; and the processing unit controlling the selected image data projected by the image projection module to move to a designated position according to a movement instruction of the user.
    Type: Application
    Filed: May 31, 2019
    Publication date: September 19, 2019
    Inventors: Yu-Hao Tseng, Kun-Hsuan Chang, Wei-Jun Wang, Ting-Wei Wu, Hsin-Chieh Cheng, Jui-Tsen Huang
  • Patent number: 10416367
    Abstract: A front light module including a light guide plate and a light source is provided. The light guide plate includes a first surface, a second surface and a light entering surface. The second surface is opposite the first surface. The light entering surface has at least one area that is adjacent to the first surface and the second surface. The light source is disposed beside the light entering surface and is configured to illuminate the light guide plate. The at least one area and an optical axis of the light source form a first angle. The first angle is less than 90 degrees. A display module is also provided.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: September 17, 2019
    Assignee: E Ink Holdings Inc.
    Inventors: Chin-Ju Hsu, Yu-Nan Pao, I-Jeng Chen, Sheng-Chieh Tai, Hsin-Tao Huang
  • Publication number: 20190267274
    Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.
    Type: Application
    Filed: May 13, 2019
    Publication date: August 29, 2019
    Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
  • Publication number: 20190252436
    Abstract: Structures and formation methods of a light sensing device are provided. The light sensing device includes a semiconductor substrate and a filter element over the semiconductor substrate. The light sensing device also includes a light sensing region below the filter element and a light shielding element over the semiconductor substrate and surrounding a lower portion of the filter element. The light sensing device further includes a dielectric element over the light shielding element and surrounding an upper portion of the filter element. A top width of the light shielding element and a bottom width of the dielectric element are different from each other.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Wei CHENG, Yi-Hsing CHU, Yin-Chieh HUANG, Chun-Hao CHOU, Kuo-Cheng LEE, Hsun-Ying HUANG, Hsin-Chi CHEN
  • Publication number: 20190252323
    Abstract: An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an antenna region. The insulating encapsulation encapsulates the integrated circuit. The redistribution circuit structure is disposed on the integrated circuit and the insulating encapsulation. The redistribution circuit structure is electrically connected to the integrated circuit, and the redistribution circuit structure includes a redistribution region and a dummy region including a plurality of dummy patterns embedded therein, wherein the antenna region includes an inductor and a wiring-free dielectric portion, and the wiring-free dielectric portion of the antenna region is between the inductor and the dummy region.
    Type: Application
    Filed: April 29, 2019
    Publication date: August 15, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
  • Patent number: 10357297
    Abstract: A bionic apparatus is provided. The bionic apparatus includes a flexible portion having a plurality of pores, a rigid portion connected with the flexible portion, and a supporting element disposed in the flexible portion. The pore size of each pore is between 50 ?m to 500 ?m. The flexible portion, the rigid portion and the supporting element are one-piece formed by a additive manufacturing process.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: July 23, 2019
    Assignees: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, NATIONAL TAIWAN UNIVERSITY HOSPITAL
    Inventors: Pei-Yi Tsai, Chih-Chieh Huang, Yi-Hung Wen, Hsin-Hsin Shen, Yi-Hung Lin, De-Yau Lin, Jui-Sheng Sun, Chuan-Sheng Chuang, An-Li Chen, Ching-Chih Lin
  • Patent number: 10326006
    Abstract: A FinFET device includes a substrate, a fin formed on the substrate, and a gate electrode crossing the fin. The gate electrode includes a head portion and a tail portion, and the tail portion is connected to the head portion and extended toward the substrate. The width of the head portion is greater than that of the tail portion.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: June 18, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Ming Peng, Chi-Wen Liu, Hsin-Chieh Huang, Yi-Ju Hsu, Horng-Huei Tseng
  • Publication number: 20190157103
    Abstract: A planarization method and a CMP method are provided. The planarization method includes providing a substrate with a first region and a second region having different degrees of hydrophobicity or hydrophilicity and performing a surface treatment to the first region to render the degrees of hydrophobicity or hydrophilicity in proximity to that of the second region. The CMP method includes providing a substrate with a first region and a second region; providing a polishing slurry on the substrate, wherein the polishing slurry and the surface of the first region have a first contact angle, and the polishing slurry and the surface of the first region have a second contact angle; modifying the surface of the first region to make a contact angle difference between the first contact angle and the second contact angle equal to or less than 30 degrees.
    Type: Application
    Filed: June 8, 2018
    Publication date: May 23, 2019
    Inventors: TUNG-KAI CHEN, CHING-HSIANG TSAI, KAO-FENG LIAO, CHIH-CHIEH CHANG, CHUN-HAO KUNG, FANG-I CHIH, HSIN-YING HO, CHIA-JUNG HSU, HUI-CHI HUANG, KEI-WEI CHEN
  • Publication number: 20190148523
    Abstract: A FinFET device includes a substrate, a fin formed on the substrate, and a gate electrode crossing the fin. The gate electrode includes a head portion and a tail portion, and the tail portion is connected to the head portion and extended toward the substrate. The width of the head portion is greater than that of the tail portion.
    Type: Application
    Filed: December 21, 2018
    Publication date: May 16, 2019
    Inventors: Yen-Ming Peng, Chi-Wen Liu, Hsin-Chieh Huang, Yi-Ju Hsu, Horng-Huei Tseng
  • Patent number: 10290530
    Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
  • Patent number: 10290604
    Abstract: Integrated circuit packages and methods of forming the same are provided. One or more redistribution layers are formed on a carrier. First connectors are formed on a first side of the RDLs. Dies are bonded to the first side of the RDLs using the first connectors. An encapsulant is formed on the first side of the RDLs around the dies. The carrier is de-bonded from the overlaying structure and second connectors are formed on a second side of the RDLs. The resulting structure in diced to form individual packages.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Lin-Chih Huang, Hung-An Teng, Hsin-Yu Chen, Tsang-Jiuh Wu, Cheng-Chieh Hsieh
  • Publication number: 20190140070
    Abstract: A semiconductor device includes a substrate, at least one active semiconductor fin, at least one first dummy semiconductor fin, and at least one second dummy semiconductor fin. The active semiconductor fin is disposed on the substrate. The first dummy semiconductor fin is disposed on the substrate. The second dummy semiconductor fin is disposed on the substrate and between the active semiconductor fin and the first dummy semiconductor fin. A top surface of the first dummy semiconductor fin and a top surface of the second dummy semiconductor fin are curved in different directions.
    Type: Application
    Filed: December 17, 2018
    Publication date: May 9, 2019
    Inventors: Chih-Sheng Li, Hsin-Chieh Huang, Chi-Wen Liu
  • Publication number: 20190131243
    Abstract: An integrated fan-out package including a die attach film, an integrated circuit component, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit component is disposed on the die attach film and includes a plurality of conductive terminals. The die attach film includes an uplifted edge which raises toward sidewalls of the integrated circuit component. The insulating encapsulation encapsulates the uplifted edge and the integrated circuit component. The redistribution circuit structure is disposed on the integrated circuit component and the insulating encapsulation, and the redistribution circuit structure is electrically connected to the conductive terminals of the integrated circuit component. A method of fabricating the integrated fan-out package are also provided.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 2, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
  • Publication number: 20190131178
    Abstract: A semiconductor device includes a substrate, a first insulating structure, a second insulating structure, at least one first active semiconductor fin, and at least one second active semiconductor fin. The first insulating structure and the second insulating structure are disposed on the substrate. The first active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the first insulating structure. The second active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the second insulating structure. The protruding portion of the first active semiconductor fin and the protruding portion of the second active semiconductor fin have different heights.
    Type: Application
    Filed: December 20, 2018
    Publication date: May 2, 2019
    Inventors: Chih-Sheng Li, Hsin-Chieh Huang, Chi-Wen Liu
  • Patent number: 10276506
    Abstract: A semiconductor device including an integrated circuit, a protection layer, and a conductive via is provided. The integrated circuit includes at least one conductive pad. The protection layer covers the integrated circuit. The protection layer includes a contact opening, and the conductive pad is exposed by the contact opening of the protection layer. The conductive via is embedded in the contact opening of the protection layer, and the conductive via is electrically connected to the conductive pad through the contact opening. A method of fabricating the above-mentioned semiconductor device and an integrated fan-out package including the above-mentioned semiconductor device are also provided.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
  • Publication number: 20190122948
    Abstract: A method includes forming a polymer layer covering a metal via in a wafer, grooving the wafer to form a trench, wherein the trench extends from a top surface of the polymer layer into the wafer, and performing a die-saw on the wafer to separate the wafer into a plurality of device dies. A kerf passes through the trench. One of the device dies is placed over a carrier. An encapsulating material is dispensed over and around the device die. The method further includes pressing and curing the encapsulating material. After the encapsulating material is cured, a sidewall of the polymer layer is tilted. A planarization is performed on the encapsulating material until the polymer layer and the metal via are exposed. A redistribution line is formed over and electrically coupled to the metal via.
    Type: Application
    Filed: December 18, 2018
    Publication date: April 25, 2019
    Inventors: Ming-Yen Chiu, Hsin-Chieh Huang, Ching Fu Chang
  • Patent number: 10247392
    Abstract: A luminous system is disclosure. The luminous system is used for projecting light to a plane and includes a luminous component and an angle-adjustable device. The luminous component is used for generating the light ray. The angle-adjustable device is used for adjusting luminous angle of the light ray. The angle-adjustable device is arranged between the plane and the luminous component and located on the route of the light ray, the angle-adjustable comprises a first lens element, and the first lens element comprises a light-emitting portion and a light-incident portion connected to the light-emitting portion. The light-including portion comprises a recess opposite to the light-emitting portion. An outer diameter of the light-emitting portion is larger than an outer diameter of the light-incident portion, and the outer diameter of the light-incident portion decreases along a direct away from the light-emitting portion.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: April 2, 2019
    Assignee: CHUN KUANG OPTICS CORP.
    Inventors: Hsin-Chieh Huang, Shun-Wen Teng, Shun Wang
  • Patent number: 10240755
    Abstract: An illumination device and the optical lens assembly thereof are provided. The illumination device includes the optical lens assembly, a light source and a driving device. The optical lens assembly includes an inner lens and an outer lens. The inner lens has a reflector having a light emission portion and a light incidence portion. An accommodating space is formed in the reflector adjacent to the light incident portion. The outer lens has a light guiding column and an outer light emission portion connected to the top of the light guiding column. The outer lens is disposed at a side of the inner lens, the light guiding column corresponds to the accommodating space, the outer light emission portion corresponds to the light emission portion. The driving device enables the outer and inner lenses to move toward or away from each other. The guiding column moves relative to the accommodating space.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: March 26, 2019
    Assignee: CHUN KUANG OPTICS CORP.
    Inventors: Hsin-Chieh Huang, Shun Wang, Shun-Wen Teng
  • Publication number: 20190074248
    Abstract: A method of manufacturing a semiconductor structure is provided. The method includes providing a substrate, disposing a die over the substrate, forming a molding over the substrate and around the die, disposing a first dielectric layer over the die and the molding, curing the first dielectric layer under a first curing condition, disposing a second dielectric layer over the first dielectric layer, and curing the first dielectric layer and the second dielectric layer under the first curing condition.
    Type: Application
    Filed: October 29, 2018
    Publication date: March 7, 2019
    Inventors: HSI-KUEI CHENG, CHIH-KANG HAN, CHING-FU CHANG, HSIN-CHIEH HUANG
  • Patent number: 10177185
    Abstract: A method for forming a high dielectric constant (high-?) dielectric layer on a substrate including performing a pre-clean process on a surface of the substrate. A chloride precursor is introduced on the surface. An oxidant is introduced to the surface to form the high-? dielectric layer on the substrate. A chlorine concentration of the high-? dielectric layer is lower than about 8 atoms/cm3.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: January 8, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Han Tsai, Horng-Huei Tseng, Hsin-Chieh Huang, Chun-Hao Chou, Kuo-Cheng Lee, Yung-Lung Hsu, Yun-Wei Cheng