Patents by Inventor Hsin-Chieh Huang

Hsin-Chieh Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220238404
    Abstract: A method includes forming a polymer layer covering a metal via in a wafer, grooving the wafer to form a trench, wherein the trench extends from a top surface of the polymer layer into the wafer, and performing a die-saw on the wafer to separate the wafer into a plurality of device dies. A kerf passes through the trench. One of the device dies is placed over a carrier. An encapsulating material is dispensed over and around the device die. The method further includes pressing and curing the encapsulating material. After the encapsulating material is cured, a sidewall of the polymer layer is tilted. A planarization is performed on the encapsulating material until the polymer layer and the metal via are exposed. A redistribution line is formed over and electrically coupled to the metal via.
    Type: Application
    Filed: April 18, 2022
    Publication date: July 28, 2022
    Inventors: Ming-Yen Chiu, Hsin-Chieh Huang, Ching Fu Chang
  • Patent number: 11387109
    Abstract: A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Lun Chang, Pin-Chuan Su, Hsin-Chieh Huang, Ming-Yuan Wu, Tzu kai Lin, Yu-Wen Wang, Che-Yuan Hsu, deseased
  • Patent number: 11362037
    Abstract: An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an antenna region. The insulating encapsulation encapsulates the integrated circuit. The redistribution circuit structure is disposed on the integrated circuit and the insulating encapsulation. The redistribution circuit structure is electrically connected to the integrated circuit, and the redistribution circuit structure includes a redistribution region and a dummy region including a plurality of dummy patterns embedded therein, wherein the antenna region includes an inductor and a wiring-free dielectric portion, and the wiring-free dielectric portion of the antenna region is between the inductor and the dummy region.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
  • Patent number: 11322419
    Abstract: A method includes forming a polymer layer covering a metal via in a wafer, grooving the wafer to form a trench, wherein the trench extends from a top surface of the polymer layer into the wafer, and performing a die-saw on the wafer to separate the wafer into a plurality of device dies. A kerf passes through the trench. One of the device dies is placed over a carrier. An encapsulating material is dispensed over and around the device die. The method further includes pressing and curing the encapsulating material. After the encapsulating material is cured, a sidewall of the polymer layer is tilted. A planarization is performed on the encapsulating material until the polymer layer and the metal via are exposed. A redistribution line is formed over and electrically coupled to the metal via.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yen Chiu, Hsin-Chieh Huang, Ching Fu Chang
  • Patent number: 11316030
    Abstract: A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: April 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Lun Chang, Shiao-Shin Cheng, Ji-Yin Tsai, Yu-Lin Tsai, Hsin-Chieh Huang, Ming-Yuan Wu, Jiun-Ming Kuo, Ming-Jie Huang, Yu-Wen Wang, Che-Yuan Hsu
  • Patent number: 11282796
    Abstract: An integrated fan-out package including a die attach film, an integrated circuit component, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit component is disposed on the die attach film and includes a plurality of conductive terminals. The die attach film includes an uplifted edge which raises toward sidewalls of the integrated circuit component. The insulating encapsulation encapsulates the uplifted edge and the integrated circuit component. The redistribution circuit structure is disposed on the integrated circuit component and the insulating encapsulation, and the redistribution circuit structure is electrically connected to the conductive terminals of the integrated circuit component. A method of fabricating the integrated fan-out package are also provided.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: March 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
  • Patent number: 11195867
    Abstract: A method for forming a high dielectric constant (high-?) dielectric layer on a substrate including performing a pre-clean process on a surface of the substrate. A chloride precursor is introduced on the surface. An oxidant is introduced to the surface to form the high-? dielectric layer on the substrate. A chlorine concentration of the high-? dielectric layer is lower than about 8 atoms/cm3.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: December 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Han Tsai, Horng-Huei Tseng, Chun-Hao Chou, Kuo-Cheng Lee, Yung-Lung Hsu, Yun-Wei Cheng, Hsin-Chieh Huang
  • Publication number: 20210335708
    Abstract: A semiconductor structure includes a die, a molding surrounding the die, a first dielectric layer disposed over the die and the molding, and a second dielectric layer disposed between the first dielectric layer and the die, and between the first dielectric layer and the molding. A material content ratio in the first dielectric layer is substantially greater than that in the second dielectric layer. In some embodiments, the material content ratio substantially inversely affects a mechanical strength of the first dielectric layer and the second dielectric layer.
    Type: Application
    Filed: July 8, 2021
    Publication date: October 28, 2021
    Inventors: HSI-KUEI CHENG, CHIH-KANG HAN, CHING-FU CHANG, HSIN-CHIEH HUANG
  • Patent number: 11143382
    Abstract: An optical lens structure includes a main body portion and a projection portion. One side of the main body portion is recessed to form an opening and a light incident portion corresponding to the opening. The main body portion has a plurality of first reflection sides and a plurality of second reflection sides arranged opposite to the plurality of first reflection sides. Each of the plurality of second reflection sides is recessed to form a recessed portion. The projection portion arranged on the other side of the main body portion. One side of the projection portion faced away from the main body portion is recessed to form a through opening and a light emitting portion. The light incident portion receives and refracts a plurality of external light beams, so that one part of the plurality of external light beams is projected to the light emitting portion.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: October 12, 2021
    Assignee: CHUAN KUANG OPTICS CORP.
    Inventors: Hsin-Chieh Huang, Sheng-Jung Lin, Shun-Wen Teng
  • Publication number: 20210288151
    Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.
    Type: Application
    Filed: May 25, 2021
    Publication date: September 16, 2021
    Inventors: Chia-Ming Chang, Chi-Wen Liu, Cheng-Chien Li, Hsin-Chieh Huang
  • Publication number: 20210257479
    Abstract: A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess.
    Type: Application
    Filed: September 15, 2020
    Publication date: August 19, 2021
    Inventors: Che-Lun Chang, Shiao-Shin Cheng, Ji-Yin Tsai, Yu-Lin Tsai, Hsin-Chieh Huang, Ming-Yuan Wu, Jiun-Ming Kuo, Ming-Jie Huang, Yu-Wen Wang, Che-Yuan Hsu
  • Publication number: 20210238132
    Abstract: An ether-bridged dication is provided with two monovalent cations bonded via a carbon chain having ether group(s). The ether-bridged dication, monovalent cations, and anions are contained together within an ionic liquid electrolyte which is applied to a charge storage device. The ether-bridged dication, the ionic liquid electrolyte, and the charge storage device have operational abilities at room temperatures or below, and a reachable working potential of 3.5 V.
    Type: Application
    Filed: April 20, 2021
    Publication date: August 5, 2021
    Inventors: Hsisheng Teng, I-wen Sun, Hsin-Chieh Huang, Yung-Che Yen, Jui-Cheng Chang
  • Patent number: 11069614
    Abstract: A semiconductor structure includes a die, a molding surrounding the die, a first dielectric layer disposed over the die and the molding, and a second dielectric layer disposed between the first dielectric layer and the die, and between the first dielectric layer and the molding. A material content ratio in the first dielectric layer is substantially greater than that in the second dielectric layer. In some embodiments, the material content ratio substantially inversely affects a mechanical strength of the first dielectric layer and the second dielectric layer.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: July 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsi-Kuei Cheng, Chih-Kang Han, Ching-Fu Chang, Hsin-Chieh Huang
  • Publication number: 20210202290
    Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.
    Type: Application
    Filed: March 15, 2021
    Publication date: July 1, 2021
    Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
  • Patent number: 11024718
    Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ming Chang, Chi-Wen Liu, Cheng-Chien Li, Hsin-Chieh Huang
  • Patent number: 11014877
    Abstract: An ether-bridged dication is provided with two monovalent cations bonded via a carbon chain having ether group(s). The ether-bridged dication, monovalent cations, and anions are contained together within an ionic liquid electrolyte which is applied to a charge storage device. The ether-bridged dication, the ionic liquid electrolyte, and the charge storage device have operational abilities at room temperatures or below, and a reachable working potential of 3.5 V.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: May 25, 2021
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Hsisheng Teng, I-wen Sun, Hsin-Chieh Huang, Yung-Che Yen, Jui-Cheng Chang
  • Patent number: 10998235
    Abstract: A semiconductor device includes a substrate, a first insulating structure, a second insulating structure, at least one first active semiconductor fin, and at least one second active semiconductor fin. The first insulating structure and the second insulating structure are disposed on the substrate. The first active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the first insulating structure. The second active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the second insulating structure. The protruding portion of the first active semiconductor fin and the protruding portion of the second active semiconductor fin have different heights.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Sheng Li, Hsin-Chieh Huang, Chi-Wen Liu
  • Publication number: 20210118804
    Abstract: A package structure is provided. The package structure includes a molding layer and a first chip having a first corner and a second corner and a second chip having a third corner and a fourth corner embedded in the molding layer. The package structure also includes first bumps electrically connected to the first chip without overlapping the first chip and the second chip. In addition, the first corner and the second corner of the first chip and the third corner and the fourth corner of the second chip form a first region in a top view, and no bump overlaps the first region.
    Type: Application
    Filed: December 28, 2020
    Publication date: April 22, 2021
    Inventors: Ming-Yen CHIU, Hsin-Chieh HUANG, Ching-Fu CHANG
  • Publication number: 20210108780
    Abstract: An optical lens structure includes a main body portion and a projection portion. One side of the main body portion is recessed to form an opening and a light incident portion corresponding to the opening. The main body portion has a plurality of first reflection sides and a plurality of second reflection sides arranged opposite to the plurality of first reflection sides. Each of the plurality of second reflection sides is recessed to form a recessed portion. The projection portion arranged on the other side of the main body portion. One side of the projection portion faced away from the main body portion is recessed to form a through opening and a light emitting portion. The light incident portion receives and refracts a plurality of external light beams, so that one part of the plurality of external light beams is projected to the light emitting portion.
    Type: Application
    Filed: September 29, 2020
    Publication date: April 15, 2021
    Inventors: Hsin-Chieh HUANG, Sheng-Jung LIN, Shun-Wen TENG
  • Publication number: 20210098434
    Abstract: An embodiment is a structure including a first package including a first die, and a molding compound at least laterally encapsulating the first die, a second package bonded to the first package with a first set of conductive connectors, the second package comprising a second die, and an underfill between the first package and the second package and surrounding the first set of conductive connectors, the underfill having a first portion extending up along a sidewall of the second package, the first portion having a first sidewall, the first sidewall having a curved portion and a planar portion.
    Type: Application
    Filed: December 14, 2020
    Publication date: April 1, 2021
    Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang