Patents by Inventor Hsin-Chieh Huang

Hsin-Chieh Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10170430
    Abstract: An integrated fan-out package including a die attach film, an integrated circuit component, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit component is disposed on the die attach film and includes a plurality of conductive terminals. The die attach film includes an uplifted edge which raises toward sidewalls of the integrated circuit component. The insulating encapsulation encapsulates the uplifted edge and the integrated circuit component. The redistribution circuit structure is disposed on the integrated circuit component and the insulating encapsulation, and the redistribution circuit structure is electrically connected to the conductive terminals of the integrated circuit component. A method of fabricating the integrated fan-out package are also provided.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
  • Patent number: 10164072
    Abstract: A semiconductor device includes a substrate, at least one active semiconductor fin, at least one first dummy semiconductor fin, and at least one second dummy semiconductor fin. The active semiconductor fin is disposed on the substrate. The first dummy semiconductor fin is disposed on the substrate. The second dummy semiconductor fin is disposed on the substrate and between the active semiconductor fin and the first dummy semiconductor fin. A top surface of the first dummy semiconductor fin and a top surface of the second dummy semiconductor fin are curved in different directions.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Sheng Li, Hsin-Chieh Huang, Chi-Wen Liu
  • Patent number: 10163745
    Abstract: A method includes forming a polymer layer covering a metal via in a wafer, grooving the wafer to form a trench, wherein the trench extends from a top surface of the polymer layer into the wafer, and performing a die-saw on the wafer to separate the wafer into a plurality of device dies. A kerf passes through the trench. One of the device dies is placed over a carrier. An encapsulating material is dispensed over and around the device die. The method further includes pressing and curing the encapsulating material. After the encapsulating material is cured, a sidewall of the polymer layer is tilted. A planarization is performed on the encapsulating material until the polymer layer and the metal via are exposed. A redistribution line is formed over and electrically coupled to the metal via.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yen Chiu, Hsin-Chieh Huang, Ching Fu Chang
  • Patent number: 10163717
    Abstract: A semiconductor device includes a substrate, a first insulating structure, a second insulating structure, at least one first active semiconductor fin, and at least one second active semiconductor fin. The first insulating structure and the second insulating structure are disposed on the substrate. The first active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the first insulating structure. The second active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the second insulating structure. The protruding portion of the first active semiconductor fin and the protruding portion of the second active semiconductor fin have different heights.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Sheng Li, Hsin-Chieh Huang, Chi-Wen Liu
  • Patent number: 10164071
    Abstract: A FinFET device includes a substrate, a fin formed on the substrate, and a gate electrode crossing the fin. The gate electrode includes a head portion and a tail portion, and the tail portion is connected to the head portion and extended toward the substrate. The width of the head portion is greater than that of the tail portion.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Ming Peng, Chi-Wen Liu, Hsin-Chieh Huang, Yi-Ju Hsu, Horng-Huei Tseng
  • Patent number: 10164059
    Abstract: A FinFET device includes a substrate, a fin formed on the substrate, and a gate electrode crossing the fin. The gate electrode includes a head portion and a tail portion, and the tail portion is connected to the head portion and extended toward the substrate. The width of the head portion is greater than that of the tail portion.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Ming Peng, Chi-Wen Liu, Hsin-Chieh Huang, Yi-Ju Hsu, Horng-Huei Tseng
  • Patent number: 10151452
    Abstract: A variable focus lighting fixture includes a fixed sleeve assembly, a moveable sleeve assembly, a light emitting unit, a lens and an actuation assembly. The moveable sleeve assembly penetrates into the fixed sleeve assembly and moves relative to the fixed sleeve assembly. The light emitting unit is secured onto the fixed sleeve assembly. The lens is secured onto the moveable sleeve assembly. The actuation assembly is connected between the moveable sleeve assembly and the fixed sleeve assembly. The actuation assembly includes a spiral curve slot and a sliding pin penetrating into the spiral curve slot. When the moveable sleeve assembly rotates along a central axis of the moveable sleeve assembly, the sliding pin moves along the spiral curve slot to drive the moveable sleeve assembly to move along the axial direction thereof. Accordingly, the projection path of the light from the light emitting unit through the lens is altered.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: December 11, 2018
    Assignee: CHUN KUANG OPTICS CORP.
    Inventors: Hsin-Chieh Huang, Shun Wang, Shun-Wen Teng
  • Publication number: 20180350784
    Abstract: An embodiment is a structure including a first package including a first die, and a molding compound at least laterally encapsulating the first die, a second package bonded to the first package with a first set of conductive connectors, the second package comprising a second die, and an underfill between the first package and the second package and surrounding the first set of conductive connectors, the underfill having a first portion extending up along a sidewall of the second package, the first portion having a first sidewall, the first sidewall having a curved portion and a planar portion.
    Type: Application
    Filed: July 31, 2018
    Publication date: December 6, 2018
    Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
  • Publication number: 20180337267
    Abstract: A FinFET device includes a substrate, a fin formed on the substrate, and a gate electrode crossing the fin. The gate electrode includes a head portion and a tail portion, and the tail portion is connected to the head portion and extended toward the substrate. The width of the head portion is greater than that of the tail portion.
    Type: Application
    Filed: July 31, 2018
    Publication date: November 22, 2018
    Inventors: Yen-Ming Peng, Chi-Wen Liu, Hsin-Chieh Huang, Yi-Ju Hsu, Horng-Huei Tseng
  • Patent number: 10128182
    Abstract: A semiconductor structure includes a substrate; a die disposed over the substrate, and including a die pad, a conductive via disposed over the die pad and a dielectric material surrounding the conductive via; a molding disposed over the substrate and surrounding the die; a lower dielectric layer disposed nearer the substrate and over the dielectric material and the molding; and an upper dielectric layer disposed further the substrate and over the lower dielectric layer, wherein a material content ratio in the upper dielectric layer is substantially greater than that in the lower dielectric layer, and the material content ratio substantially inversely affects a mechanical strength of the upper dielectric layer and the lower dielectric layer.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: November 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsi-Kuei Cheng, Chih-Kang Han, Ching-Fu Chang, Hsin-Chieh Huang
  • Patent number: 10115686
    Abstract: A method of fabricating a semiconductor structure includes: forming a conductive layer on a first insulating layer; etching a portion of the conductive layer to expose a portion of the first insulating layer; deforming a surface of the portion of the first insulating layer to form a rough surface of the first insulating layer; and removing a residue of the conductive layer on the rough surface of the first insulating layer.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: October 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Li Huang, Jheng-Jie Wong, Hsiang-Sheng Su, Tsung-Lung Huang, Kuo-Chio Liu, Hsin-Chieh Huang, De-Dui Marvin Liao, Chin-Yu Ku, Chen-Shien Chen
  • Patent number: 10109589
    Abstract: An integrated fan-out package including a die attach film, an integrated circuit component, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit component is disposed on the die attach film and includes a plurality of conductive terminals. The die attach film includes an uplifted edge which raises toward sidewalls of the integrated circuit component. The insulating encapsulation encapsulates the uplifted edge and the integrated circuit component. The redistribution circuit structure is disposed on the integrated circuit component and the insulating encapsulation, and the redistribution circuit structure is electrically connected to the conductive terminals of the integrated circuit component. A method of fabricating the integrated fan-out package are also provided.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: October 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
  • Patent number: 10083921
    Abstract: Some embodiments relate to a die that has been formed by improved dicing techniques. The die includes a substrate which includes upper and lower substrate surfaces with a vertical substrate sidewall extending therebetween. The vertical substrate sidewall corresponds to an outermost edge of the substrate. A device layer is arranged over the upper substrate surface. A crack stop is arranged over an upper surface of the device layer and has an outer perimeter that is spaced apart laterally from the vertical substrate sidewall. The die exhibits a tapered sidewall extending downward through at least a portion of the device layer to meet the vertical substrate sidewall.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: September 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Syuan Lin, Jiun-Lei Jerry Yu, Ming-Cheng Lin, Hsin-Chieh Huang, Chao-Hsiung Wang
  • Patent number: 10077883
    Abstract: An illumination device includes an optical component and a light-emitting module. The optical component includes a light-transmitting body, a first optical unit, and a second optical unit. The first optical unit has a light input surface and a plurality of surrounding structures surrounding the light input surface and arranged in a pattern of concentric circles, and each surrounding structure has a first surrounding surface and a second surrounding surface. The second optical unit has a spiral structure surrounding the light output surface of the light-transmitting body and a surrounding frame surrounding the light output surface of the light-transmitting body and the spiral structure, and a relative height from a topmost surface of the spiral structure to the light output surface of the light-transmitting body is increased gradually from inner to outer. The light-emitting module is disposed under the light input surface of the first optical unit.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: September 18, 2018
    Assignee: CHUN KUANG OPTICS CORP.
    Inventors: Hsin-Chieh Huang, Shun-Wen Teng, Shun Wang
  • Patent number: 10050148
    Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. A topmost location of the epitaxy structure has an n-type impurity concentration lower than an n-type impurity concentration of a location of the epitaxy structure below the topmost location.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ming Chang, Chi-Wen Liu, Hsin-Chieh Huang, Cheng-Chien Li
  • Patent number: 10037961
    Abstract: An integrated fan-out package including an integrated circuit, an insulating encapsulation, a plurality of conductive through vias, and a redistribution circuit structure is provided. The integrated circuit includes a plurality of conductive terminals. The insulating encapsulation encapsulates sidewalls of the integrated circuit. The conductive through vias penetrate in the insulating encapsulation. The redistribution circuit structure is disposed on the integrated circuit, the conductive through vias and the insulating encapsulation. The redistribution conductive layer is electrically connected to the conductive terminals and the conductive through vias. A plurality of first contact surfaces of the conductive terminals and a plurality of second contact surfaces of the conductive through vias are in contact with the redistribution circuit structure, and a roughness of the first contact surfaces and the second contact surfaces ranges from 100 angstroms to 500 angstroms.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: July 31, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
  • Patent number: 10032873
    Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: July 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ming Chang, Chi-Wen Liu, Cheng-Chien Li, Hsin-Chieh Huang
  • Publication number: 20180204780
    Abstract: A method includes forming a polymer layer covering a metal via in a wafer, grooving the wafer to form a trench, wherein the trench extends from a top surface of the polymer layer into the wafer, and performing a die-saw on the wafer to separate the wafer into a plurality of device dies. A kerf passes through the trench. One of the device dies is placed over a carrier. An encapsulating material is dispensed over and around the device die. The method further includes pressing and curing the encapsulating material. After the encapsulating material is cured, a sidewall of the polymer layer is tilted. A planarization is performed on the encapsulating material until the polymer layer and the metal via are exposed. A redistribution line is formed over and electrically coupled to the metal via.
    Type: Application
    Filed: March 19, 2018
    Publication date: July 19, 2018
    Inventors: Ming-Yen Chiu, Hsin-Chieh Huang, Ching Fu Chang
  • Patent number: 10025077
    Abstract: A device for measuring solution concentration includes housing, a catadioptric structure, an electromagnetic radiation emitter and an electromagnetic radiation detector. The housing is formed with a detecting part for receiving a solution to be detected. The catadioptric structure is received in the housing, and includes a ray entrance portion, a first total internal reflection part, a second total internal reflection part and a ray exit portion. An accommodation part corresponds to the detecting part. The emitter is disposed at one side of the ray entrance portion, and a ray sequentially passes the ray entrance portion, the detecting part, the solution to be detected, and the first total internal reflection part. Then, the ray is totally internally reflected and converged to the second total internal reflection part, and is reflected again. Finally, the ray passes the ray exit portion and is received by the detector.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: July 17, 2018
    Assignee: CHUN KUANG OPTICS CORP.
    Inventors: Hsin-Chieh Huang, Cheng-Yu Huang, Shun Wang, Shun-Wen Teng
  • Publication number: 20180182673
    Abstract: A semiconductor device includes a substrate, a first insulating structure, a second insulating structure, at least one first active semiconductor fin, and at least one second active semiconductor fin. The first insulating structure and the second insulating structure are disposed on the substrate. The first active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the first insulating structure. The second active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the second insulating structure. The protruding portion of the first active semiconductor fin and the protruding portion of the second active semiconductor fin have different heights.
    Type: Application
    Filed: February 26, 2018
    Publication date: June 28, 2018
    Inventors: Chih-Sheng Li, Hsin-Chieh Huang, Chi-Wen Liu