Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first III-V compound layer disposed on the substrate, a second III-V compound layer disposed on the first III-V compound layer, a p-type doped III-V compound layer disposed on the second III-V compound layer, a gate disposed over the p-type doped III-V compound layer, a source and a drain disposed on opposite sides of the gate, and a dielectric layer disposed between the p-type doped III-V compound layer and the gate. A method for forming the above semiconductor device is also provided.

Abstract: A semiconductor structure includes a substrate, a conductive via and a first insulation layer. The conductive via is through the substrate. The first insulation layer is between the substrate and the conductive via. A first surface of the first insulation layer facing the substrate and a second surface of the first insulation layer facing the conductive via are extended along different directions.

Abstract: An uninterruptible power apparatus is coupled between a power grid and a load. The uninterruptible power apparatus includes a bypass path, a power conversion module, and a control module. The bypass path is coupled to the power grid through a grid terminal, and coupled to the load through a load terminal. The control module turns off a first thyristor and a second thyristor by injecting a second voltage into the load terminal during a forced commutation period. The control module calculates a magnetic flux offset amount based on an error amount between the second voltage and a voltage command, and provides a compensation command in response to the magnetic flux offset amount. The control module controls the DC/AC conversion circuit to provide a third voltage to the load terminal based on the compensation command and the voltage command.

Abstract: A device includes a first III-V compound layer, a second III-V compound layer, a dielectric layer, a contact, a metal-containing layer, and a metal contact. The second III-V compound layer is over the first III-V compound layer. The dielectric layer is over the second III-V compound layer. The contact extends through the dielectric layer to the second III-V compound layer. The contact is in contact with a top surface of the dielectric layer and an inner sidewall of the dielectric layer. The metal-containing layer is over and in contact with the contact, and a portion of the metal-containing layer is directly above the dielectric layer. The metal contact is over and in contact with the metal-containing layer.

Abstract: A method for forming a high electron mobility transistor (HEMT) includes forming a buffer layer on a transparent substrate. The method further includes forming a barrier layer on the buffer layer. A channel region is formed in the buffer layer adjacent to the interface between the buffer layer and the barrier layer. The method further includes forming a dielectric layer on the barrier layer. The method further includes forming source/drain electrodes through the dielectric layer and the barrier layer and disposed on the buffer layer. The method further includes forming a shielding layer conformally covering the dielectric layer and the source/drain electrodes. The method further includes performing a thermal process on the source/drain electrodes.

Abstract: A semiconductor device includes a compound semiconductor layer disposed on a substrate, a protection layer disposed on the compound semiconductor layer, and a source electrode, a drain electrode and a gate electrode penetrating the protection layer and on the compound semiconductor layer, wherein the gate electrode is disposed between the source electrode and the drain electrode. The semiconductor device also includes a plurality of field plates disposed over the protection layer and between the gate electrode and the drain electrode, wherein the plurality of field plates are separated from each other.

Abstract: A device includes a first III-V compound layer, a second III-V compound layer, source and drain structures, a gate structure, and a gate field plate. The second III-V compound layer is over the first III-V compound layer. The source and drain structures are over the second III-V compound layer and spaced apart from each other. The gate structure is over the second III-V compound layer and between the source and drain structures. The gate field plate is over the second III-V compound. From a top view the gate field plate forms a strip pattern interposing a stripe pattern of the gate structure and a stripe pattern of the drain structure.

Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, source and drain structures over the second III-V compound layer and spaced apart from each other, a gate structure over the second III-V compound layer and between the source and drain structures, a gate field plate over the second III-V compound layer and between the gate structure and the drain structure, and an etch stop layer over the drain structure and spaced apart from the gate field plate.

Abstract: The present disclosure provides an organic light emitting display panel, a method for manufacturing the same, and an organic light emitting display apparatus. The organic light emitting display panel includes an array substrate, a color filter substrate and an encapsulation structure; the encapsulation structure includes a sealing frame and/or a sealing layer disposed between the array substrate and the color filter substrate, and the array substrate and the color filter substrate are adhesively fixed through the sealing frame and/or the sealing layer; wherein the sealing frame is formed by curing a frame sealant and is located in a frame area of the array substrate and the color filter substrate, and the sealing layer is formed by curing a filling adhesive and is located in a display area of the array substrate and the color filter substrate.

Abstract: The present disclosure provides an organic light emitting display panel and an organic light emitting display apparatus. The organic light emitting display panel includes an array substrate, a color filter substrate and a transparent filling layer; the array substrate includes a substrate and an organic light emitting layer and a thin film encapsulation layer sequentially formed on the substrate, and the color filter substrate includes a cover plate and a color filter layer and an organic protective layer sequentially formed on the cover plate; the array substrate and the color filter substrate are disposed opposite to each other, the organic light emitting layer includes a plurality of OLED pixel units, the color filter layer includes a plurality of color-resist units; wherein, the transparent filling layer is disposed in a gap between the array substrate and the color filter substrate for reducing light deflection.

Abstract: A device includes a first III-V compound layer, a second III-V compound layer, a dielectric layer, a contact, a metal-containing layer, and a metal contact. The second III-V compound layer is over the first III-V compound layer. The dielectric layer is over the second III-V compound layer. The contact extends through the dielectric layer to the second III-V compound layer. The contact is in contact with a top surface of the dielectric layer and an inner sidewall of the dielectric layer. The metal-containing layer is over and in contact with the contact, and a portion of the metal-containing layer is directly above the dielectric layer. The metal contact is over and in contact with the metal-containing layer.

Abstract: A semiconductor device includes and an active region and a peripheral region. The peripheral region includes a seal region. The semiconductor device includes a substrate and a seed layer one the substrate. The semiconductor device also includes a GaN-containing composite layer on the seed layer, and the GaN-containing composite layer is disposed in the active region and the peripheral region. The semiconductor device also includes a gate electrode, a source electrode and a drain electrode disposed on the GaN-containing composite layer within the active region. The source electrode and the drain electrode are disposed at two opposite sides of the gate electrode. The semiconductor device further includes a sealing structure, and the sealing structure includes a barrier structure and a seal component in the seal region. The barrier structure is disposed around the active region. The barrier structure penetrates the GaN-containing composite layer and the seed layer.

Abstract: A semiconductor device includes a base and a conductive layer to form a composite substrate. The conductive layer covers a surface of the base. The semiconductor device also includes a dielectric layer covering the conductive layer. The conductive layer is disposed between the dielectric layer and the base. The semiconductor device further includes a GaN-containing composite layer, a gate electrode disposed over the GaN-containing composite layer, a source electrode and a drain electrode disposed on the GaN-containing composite layer. The source electrode and the drain electrode are disposed at two opposite sides of the gate electrode. In addition, a method for manufacturing the semiconductor device with a composite substrate is provided.

Abstract: A semiconductor structure is provided. The semiconductor structure includes: a substrate; a source structure and a drain structure disposed on the substrate; a gate structure disposed on the substrate and between the source structure and the drain structure; a first field plate disposed on the substrate; a first oxide layer disposed between the substrate and the first field plate; a second field plate disposed on the first field plate, wherein the second field plate is closer to the drain structure than the first field plate; a planarized second oxide layer disposed between the first oxide layer and the second field plate; and a third field plate disposed on the second field plate, wherein the third field plate is closer to the drain structure than the second field plate.

Abstract: A semiconductor device includes a compound semiconductor layer disposed on a substrate, a protection layer disposed on the compound semiconductor layer, and a source electrode, a drain electrode and a gate electrode penetrating the protection layer and on the compound semiconductor layer, wherein the gate electrode is disposed between the source electrode and the drain electrode. The semiconductor device also includes a plurality of field plates disposed over the protection layer and between the gate electrode and the drain electrode, wherein the plurality of field plates are separated from each other.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first III-V compound layer disposed on the substrate, a second III-V compound layer disposed on the first III-V compound layer, a p-type doped III-V compound layer disposed on the second III-V compound layer, a gate disposed over the p-type doped III-V compound layer, a source and a drain disposed on opposite sides of the gate, and a dielectric layer disposed between the p-type doped III-V compound layer and the gate. A method for forming the above semiconductor device is also provided.

Abstract: A semiconductor device includes a compound semiconductor layer disposed on a substrate, a protection layer disposed on the compound semiconductor layer, and a source electrode, a drain electrode and a gate electrode penetrating the protection layer and on the compound semiconductor layer, wherein the gate electrode is disposed between the source electrode and the drain electrode. The semiconductor device also includes a plurality of field plates disposed over the protection layer and between the gate electrode and the drain electrode, wherein the plurality of field plates are separated from each other. A method for fabricating the semiconductor device is also provided.

Abstract: A semiconductor structure includes a substrate, a gate electrode, a first dielectric layer, a gate metal layer, a source structure, and a drain structure. The first dielectric layer has a first opening exposing the gate electrode and a second opening, and the depth of the second opening is greater than the depth of the first opening. The gate metal layer conformally covers the top surface of the first dielectric layer, the first opening, and the second opening to serve as a gate field plate. A first portion of the gate metal layer at the bottom of the first opening is higher than a second portion of the gate metal layer at the bottom of the second opening. The source structure and the drain structure are disposed at opposite sides of the gate structure, wherein the second opening is disposed between the gate electrode and the drain structure.

Abstract: A semiconductor device includes and an active region and a peripheral region. The peripheral region includes a seal region. The semiconductor device includes a substrate and a seed layer one the substrate. The semiconductor device also includes a GaN-containing composite layer on the seed layer, and the GaN-containing composite layer is disposed in the active region and the peripheral region. The semiconductor device also includes a gate electrode, a source electrode and a drain electrode disposed on the GaN-containing composite layer within the active region. The source electrode and the drain electrode are disposed at two opposite sides of the gate electrode. The semiconductor device further includes a sealing structure, and the sealing structure includes a barrier structure and a seal component in the seal region. The barrier structure is disposed around the active region. The barrier structure penetrates the GaN-containing composite layer and the seed layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes: a substrate; a source structure and a drain structure disposed on the substrate; a gate structure disposed on the substrate and between the source structure and the drain structure; a first field plate disposed on the substrate; a first oxide layer disposed between the substrate and the first field plate; a second field plate disposed on the first field plate, wherein the second field plate is closer to the drain structure than the first field plate; a planarized second oxide layer disposed between the first oxide layer and the second field plate; and a third field plate disposed on the second field plate, wherein the third field plate is closer to the drain structure than the second field plate.