Patents by Inventor Hsin-Chih Lin
Hsin-Chih Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210151571Abstract: A semiconductor structure is provided. The semiconductor structure includes: a substrate; a source structure and a drain structure disposed on the substrate; a gate structure disposed on the substrate and between the source structure and the drain structure; a first field plate disposed on the substrate; a first oxide layer disposed between the substrate and the first field plate; a second field plate disposed on the first field plate, wherein the second field plate is closer to the drain structure than the first field plate; a planarized second oxide layer disposed between the first oxide layer and the second field plate; and a third field plate disposed on the second field plate, wherein the third field plate is closer to the drain structure than the second field plate.Type: ApplicationFiled: November 20, 2019Publication date: May 20, 2021Applicant: Vanguard International Semiconductor CorporationInventors: Cheng-Wei CHOU, Hsin-Chih LIN, Yu-Chieh CHOU, Chang-Xiang HUNG
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Patent number: 10998434Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first III-V compound layer disposed on the substrate, a second III-V compound layer disposed on the first III-V compound layer, a p-type doped III-V compound layer disposed on the second III-V compound layer, a gate disposed over the p-type doped III-V compound layer, a source and a drain disposed on opposite sides of the gate, and a dielectric layer disposed between the p-type doped III-V compound layer and the gate. A method for forming the above semiconductor device is also provided.Type: GrantFiled: December 22, 2017Date of Patent: May 4, 2021Assignee: Vanguard International Semiconductor CorporationInventors: Hsin-Chih Lin, Shin-Cheng Lin, Yung-Hao Lin
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Publication number: 20210089740Abstract: The disclosure discloses a display panel and a display device, comprising: an OLED substrate; an optical fingerprint sensor; a first quarter-wave plate; a first linear polarizer provided on one side, away from the OLED substrate, of the first quarter-wave plate; a second quarter-wave plate provided on one side, facing to the optical fingerprint sensor, of the OLED substrate; a second linear polarizer provided on one side, facing away from the OLED substrate, of the second quarter-wave plate and positioned between the second quarter-wave plate and the optical fingerprint sensor.Type: ApplicationFiled: April 21, 2020Publication date: March 25, 2021Applicant: EverDisplay Optronics (Shanghai) LimitedInventors: Zhao WANG, Zhijiang HE, Hsin Chih LIN, Jia WEI
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Patent number: 10903350Abstract: A semiconductor device includes a first composite III-V group compound semiconductor layer disposed on a composite substrate, and a second III-V group compound semiconductor layer disposed on the first composite III-V group compound semiconductor layer. The semiconductor device also includes a gate structure disposed on the second III-V group compound semiconductor layer, and a source electrode and a drain electrode disposed on the second III-V group compound semiconductor layer and at opposite sides of the gate structure. The semiconductor device further includes a field plate disposed between the gate structure and the drain electrode, and a conductive structure penetrating through the second III-V group compound semiconductor layer and the first composite III-V group compound semiconductor layer, wherein the field plate is electrically connected to the composite substrate through the conductive structure.Type: GrantFiled: February 21, 2019Date of Patent: January 26, 2021Assignee: Vanguard International Semiconductor CorporationInventors: Cheng-Wei Chou, Hsin-Chih Lin, Yu-Chieh Chou
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Publication number: 20210013120Abstract: A semiconductor device includes a base and a conductive layer to form a composite substrate. The conductive layer covers a surface of the base. The semiconductor device also includes a dielectric layer covering the conductive layer. The conductive layer is disposed between the dielectric layer and the base. The semiconductor device further includes a GaN-containing composite layer, a gate electrode disposed over the GaN-containing composite layer, a source electrode and a drain electrode disposed on the GaN-containing composite layer. The source electrode and the drain electrode are disposed at two opposite sides of the gate electrode. In addition, a method for manufacturing the semiconductor device with a composite substrate is provided.Type: ApplicationFiled: July 11, 2019Publication date: January 14, 2021Applicant: Vanguard International Semiconductor CorporationInventors: Yu-Chieh CHOU, Hsin-Chih LIN
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Patent number: 10867993Abstract: A semiconductor structure includes a substrate, a first III-V compound layer, a second III-V compound layer, a third III-V compound layer, and a fourth III-V compound layer. The top of the substrate includes a first region and a second region. The first III-V compound layer is in the first region. The second III-V compound layer is disposed over the first III-V compound layer. A first carrier channel is formed between the first III-V compound layer and the second III-V compound layer. The second III-V compound layer has a first thickness. The third III-V compound layer is in the second region. The fourth III-V compound layer is disposed over the third III-V compound layer. A second carrier channel is formed between the fourth III-V compound layer and the third III-V compound layer. The fourth III-V compound layer has a second thickness less than the first thickness.Type: GrantFiled: March 20, 2020Date of Patent: December 15, 2020Assignee: Vanguard International Semiconductor CorporationInventors: Fu-Hsin Chen, Shin-Cheng Lin, Yung-Hao Lin, Hsin-Chih Lin
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Publication number: 20200373420Abstract: A semiconductor structure includes a substrate, a gate electrode, a first dielectric layer, a gate metal layer, a source structure, and a drain structure. The first dielectric layer has a first opening exposing the gate electrode and a second opening, and the depth of the second opening is greater than the depth of the first opening. The gate metal layer conformally covers the top surface of the first dielectric layer, the first opening, and the second opening to serve as a gate field plate. A first portion of the gate metal layer at the bottom of the first opening is higher than a second portion of the gate metal layer at the bottom of the second opening. The source structure and the drain structure are disposed at opposite sides of the gate structure, wherein the second opening is disposed between the gate electrode and the drain structure.Type: ApplicationFiled: May 20, 2019Publication date: November 26, 2020Applicant: Vanguard International Semiconductor CorporationInventors: Yu-Chieh CHOU, Hsin-Chih LIN, Chang-Xiang HUNG
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Patent number: 10833131Abstract: A touch control display panel includes a display area and a border area, wherein the border area is extended along a first direction, and the border area and the display area are arranged along a second direction perpendicular to the first direction. The border area includes a flexible-printed-circuit (FPC) touch control driver bonding area and a chip-on-film (COF) display driver bonding area, wherein the FPC touch control driver bonding area and the COF display driver bonding area are arranged along the first direction.Type: GrantFiled: March 25, 2019Date of Patent: November 10, 2020Assignee: EverDisplay Optronics (Shanghai) LimitedInventors: Hsin Chih Lin, Tangliang Zhao
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Publication number: 20200328288Abstract: A method for forming a high electron mobility transistor (HEMT) includes forming a buffer layer on a transparent substrate. The method further includes forming a barrier layer on the buffer layer. A channel region is formed in the buffer layer adjacent to the interface between the buffer layer and the barrier layer. The method further includes forming a dielectric layer on the barrier layer. The method further includes forming source/drain electrodes through the dielectric layer and the barrier layer and disposed on the buffer layer. The method further includes forming a shielding layer conformally covering the dielectric layer and the source/drain electrodes. The method further includes performing a thermal process on the source/drain electrodes.Type: ApplicationFiled: June 25, 2020Publication date: October 15, 2020Applicant: Vanguard International Semiconductor CorporationInventors: Cheng-Wei CHOU, Hsin-Chih LIN
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Publication number: 20200312983Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, source and drain structures over the second III-V compound layer and spaced apart from each other, a gate structure over the second III-V compound layer and between the source and drain structures, a gate field plate over the second III-V compound layer and between the gate structure and the drain structure, and an etch stop layer over the drain structure and spaced apart from the gate field plate.Type: ApplicationFiled: June 15, 2020Publication date: October 1, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jheng-Sheng YOU, Hsin-Chih LIN, Kun-Ming HUANG, Lieh-Chuan CHEN, Po-Tao CHU, Shen-Ping WANG, Chien-Li KUO
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Publication number: 20200273976Abstract: A semiconductor device includes a first composite III-V group compound semiconductor layer disposed on a composite substrate, and a second III-V group compound semiconductor layer disposed on the first composite III-V group compound semiconductor layer. The semiconductor device also includes a gate structure disposed on the second III-V group compound semiconductor layer, and a source electrode and a drain electrode disposed on the second III-V group compound semiconductor layer and at opposite sides of the gate structure. The semiconductor device further includes a field plate disposed between the gate structure and the drain electrode, and a conductive structure penetrating through the second III-V group compound semiconductor layer and the first composite III-V group compound semiconductor layer, wherein the field plate is electrically connected to the composite substrate through the conductive structure.Type: ApplicationFiled: February 21, 2019Publication date: August 27, 2020Applicant: Vanguard International Semiconductor CorporationInventors: Cheng-Wei CHOU, Hsin-Chih LIN, Yu-Chieh CHOU
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Patent number: 10741666Abstract: A method for forming a high electron mobility transistor (HEMT) includes forming a buffer layer on a transparent substrate. The method further includes forming a barrier layer on the buffer layer. A channel region is formed in the buffer layer adjacent to the interface between the buffer layer and the barrier layer. The method further includes forming a dielectric layer on the barrier layer. The method further includes forming source/drain electrodes through the dielectric layer and the barrier layer and disposed on the buffer layer. The method further includes forming a shielding layer conformally covering the dielectric layer and the source/drain electrodes. The method further includes performing a thermal process on the source/drain electrodes.Type: GrantFiled: November 19, 2018Date of Patent: August 11, 2020Assignee: Vanguard International Semiconductor CorporationInventors: Cheng-Wei Chou, Hsin-Chih Lin
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Publication number: 20200219870Abstract: A semiconductor structure includes a substrate, a first III-V compound layer, a second III-V compound layer, a third III-V compound layer, and a fourth III-V compound layer. The top of the substrate includes a first region and a second region. The first III-V compound layer is in the first region. The second III-V compound layer is disposed over the first III-V compound layer. A first carrier channel is formed between the first III-V compound layer and the second III-V compound layer. The second III-V compound layer has a first thickness. The third III-V compound layer is in the second region. The fourth III-V compound layer is disposed over the third III-V compound layer. A second carrier channel is formed between the fourth III-V compound layer and the third III-V compound layer. The fourth III-V compound layer has a second thickness less than the first thickness.Type: ApplicationFiled: March 20, 2020Publication date: July 9, 2020Applicant: Vanguard International Semiconductor CorporationInventors: Fu-Hsin CHEN, Shin-Cheng LIN, Yung-Hao LIN, Hsin-Chih LIN
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Patent number: 10707322Abstract: A semiconductor device includes a channel layer disposed over a substrate, a barrier layer disposed over the channel layer, a gate electrode disposed over the barrier layer, and a pair of source/drain electrodes disposed on opposite sides of the gate electrode. The pair of source/drain electrodes extend through at least portions of the barrier layer. The semiconductor device also includes a lining layer conformally disposed on bottom portions of the pair of source/drain electrodes.Type: GrantFiled: October 22, 2018Date of Patent: July 7, 2020Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Chih-Yen Chen, Shin-Cheng Lin, Hsin-Chih Lin
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Patent number: 10692857Abstract: A semiconductor structure includes a substrate, a first III-V compound layer, a second III-V compound layer, a third III-V compound layer, and a fourth III-V compound layer. The top of the substrate includes a first region and a second region. The first III-V compound layer is in the first region. The second III-V compound layer is disposed over the first III-V compound layer. A first carrier channel is formed between the first III-V compound layer and the second III-V compound layer. The second III-V compound layer has a first thickness. The third III-V compound layer is in the second region. The fourth III-V compound layer is disposed over the third III-V compound layer. A second carrier channel is formed between the fourth III-V compound layer and the third III-V compound layer. The fourth III-V compound layer has a second thickness less than the first thickness.Type: GrantFiled: May 8, 2018Date of Patent: June 23, 2020Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Fu-Hsin Chen, Shin-Cheng Lin, Yung-Hao Lin, Hsin-Chih Lin
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Patent number: 10686054Abstract: A semiconductor device includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, a source contact and a drain contact over the second III-V compound layer, a gate contact over the second III-V compound layer and between the source contact and the drain contact, a gate field plate over the second III-V compound layer, a first etch stop layer over the source contact, and a second etch stop layer over the drain contact and separated from the first etch stop layer.Type: GrantFiled: November 19, 2018Date of Patent: June 16, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jheng-Sheng You, Hsin-Chih Lin, Kun-Ming Huang, Lieh-Chuan Chen, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo
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Publication number: 20200161447Abstract: A method for forming a high electron mobility transistor (HEMT) includes forming a buffer layer on a transparent substrate. The method further includes forming a barrier layer on the buffer layer. A channel region is formed in the buffer layer adjacent to the interface between the buffer layer and the barrier layer. The method further includes forming a dielectric layer on the barrier layer. The method further includes forming source/drain electrodes through the dielectric layer and the barrier layer and disposed on the buffer layer. The method further includes forming a shielding layer conformally covering the dielectric layer and the source/drain electrodes. The method further includes performing a thermal process on the source/drain electrodes.Type: ApplicationFiled: November 19, 2018Publication date: May 21, 2020Applicant: Vanguard International Semiconductor CorporationInventors: Cheng-Wei CHOU, Hsin-Chih LIN
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Patent number: 10651033Abstract: A method for manufacturing a semiconductor device structure is provided. The method includes providing a base substrate and forming a buffer layer on the base substrate. The method also includes forming a patterned silicon layer on the buffer layer. The patterned silicon layer has an opening to expose a portion of the buffer layer. The method further includes epitaxially growing a patterned channel layer and a patterned barrier layer on a top surface of the patterned silicon layer sequentially. In addition, the method includes forming a gate electrode on the patterned barrier layer.Type: GrantFiled: January 7, 2019Date of Patent: May 12, 2020Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Cheng-Wei Chou, Hsin-Chih Lin, Yu-Chieh Chou
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Publication number: 20200127116Abstract: A semiconductor device includes a channel layer disposed over a substrate, a barrier layer disposed over the channel layer, a gate electrode disposed over the barrier layer, and a pair of source/drain electrodes disposed on opposite sides of the gate electrode. The pair of source/drain electrodes extend through at least portions of the barrier layer. The semiconductor device also includes a lining layer conformally disposed on bottom portions of the pair of source/drain electrodes.Type: ApplicationFiled: October 22, 2018Publication date: April 23, 2020Applicant: Vanguard International Semiconductor CorporationInventors: Chih-Yen CHEN, Shin-Cheng LIN, Hsin-Chih LIN
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Patent number: 10629475Abstract: A method for forming a semiconductor device is provided. A substrate is provided. An epitaxial layer is formed on the substrate. An insulation region and an active region are defined on the upper surface of the epitaxial layer. An insulation structure is formed within the insulation region by an ion implantation process and an etching process, wherein the insulation structure includes a first insulation structure and a second insulation structure. A gate is formed on the epitaxial layer and is disposed within the active region. A source and a drain are formed on opposite sides of the gate and within the active region. A semiconductor device is also provided.Type: GrantFiled: December 22, 2017Date of Patent: April 21, 2020Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Hsin-Chih Lin, Shin-Cheng Lin, Yung-Hao Lin