Abstract: A method for encapsulating an integrated circuit chip is described. An integrated circuit chip is attached to a substrate. A dam is formed surrounding the integrated circuit chip. At least one corner of the integrated circuit chip is covered with a stress buffering material. The integrated circuit chip and all of the substrate within the dam are coated with an encapsulation material wherein the encapsulation material covers the stress buffering material and wherein the stress buffering material prevents delamination of the encapsulation material at the corners of the integrated circuit chip.

Abstract: A multi-layered semiconductor structure with free areas limiting the placement of test keys. First and second scribe lines intersect to define one corner point of a die. The first and second scribe lines are part of the multilayered structure and at least one layer of the multi-layer structure is a low-k dielectric layer. Free area A1 is defined on the first scribe line and is defined by the equation A1=D1×S1, where D1 is the distance from the corner point of the die toward the main area of the die, and S1 is the width of the first scribe line. Free area As is defined at the intersection of the first scribe line and the second scribe line adjacent the die and is defined by the equation As=S1×S2, where S2 is the width of the second scribe line.

Abstract: A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CF4, SF4, and H2 and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.

Abstract: A stencil design for solder paste printing, or other metal stencil printing, is disclosed. A stencil for stencil printing of solder onto a semiconductor wafer for semiconductor wafer bumping includes a substrate. The substrate has a hole defined therein substantially shaped to correspond to and receptive to the semiconductor wafer. An interior edge of the substrate surrounds the hole, and has an upper lip under which the semiconductor wafer is positioned. The upper lip of the interior edge of the substrate surrounding the hole substantially prevents the solder from flowing onto sides and a bottom of the semiconductor wafer during stencil printing of the solder. The cross-profile shape of the upper lip may in one embodiment be rectangular, whereas in another embodiment be triangular.

Abstract: A Ferris wheel-like stripping or cleaning mechanism that can be used in semiconductor fabrication, such as in photoresist or other stripping, or wafer or other cleaning, is disclosed. A stripping mechanism can include a container to hold a chemical, such as a photoresist stripping chemical, a wafer cleaning chemical, or another type of chemical. The mechanism can also include a component to move semiconductor wafers through the chemical in the container in a Ferris wheel-like motion. The component may include wafer holders for the wafers that are swivably mounted about an axis of rotation. As the one or more wafer holders rotate about the axis of rotation through the chemical in the container, the wafer holders remain in a substantially constant vertical and horizontal orientation.

Abstract: A new method is provided for the creation of a solder bump. Conventional methods are initially followed, creating a patterned layer of Under Bump Metal over the surface of a contact pad. A layer of photoresist is next deposited, this layer of photoresist is patterned and developed creating a resist mask having a T-shape opening aligned with the contact pad. This T-shaped opening is filled with a solder compound, creating a T-shaped layer of solder compound on the surface of the layer of UBM. The layer of photoresist is removed, exposing the created T-shaped layer of solder compound, further exposing the layer of UBM. The layer of UBM is etched using the T-shaped layer of solder compound as a mask. Reflow of the solder compound results in creating a solder ball.

Abstract: A new method is provided for the creation of a solder bump. Conventional methods are initially followed, creating a patterned layer of Under Bump Metal over the surface of a contact pad. A layer of photoresist is next deposited, this layer of photoresist is patterned and developed creating a resist mask having a T-shape opening aligned with the contact pad. This T-shaped opening is filled with a solder compound, creating a T-shaped layer of solder compound on the surface of the layer of UBM. The layer of photoresist is removed, exposing the Created T-shaped layer of solder compound, further exposing the layer of UBM. The layer of UBM is etched using the T-shaped layer of solder compound as a mask. Reflow of the solder compound results in creating a solder ball.

Abstract: A method of forming a bump on a substrate such as a semiconductor wafer or flip chip. The method includes the act of providing a semiconductor device having a contact pad and having an upper passivation layer and an opening formed in the upper passivation layer exposing a portion of the contact pad. An under bump metallurgy is deposited over the upper passivation layer and the contact pad. An electrically conductive redistribution trace is deposited over the under bump metallurgy. A photoresist layer is deposited, patterned and developed to provide portions selectively protecting the electrically conductive redistribution trace and the under bump metallurgy. Excess portions of the electrically conductive redistribution trace and under bump metallurgy not protected by the photoresist are removed.

Abstract: A new method is provided for the processing of metals, most notably copper, such that damage to exposed surfaces of these metals is prevented. During a step of semiconductor processing, which results in exposing a metal surface to a wet substance having a pH value, a voltage is applied to the metal that is exposed. The value of the applied voltage can, dependent on the value of the pH constant of the wet substance, be selected such that the exposed metal surface is protected against alkaline effects of the wet substance.

Abstract: A DFR laminating and PET removing system which is capable of both laminating a dry film resist (DFR) layer on a semiconductor wafer and removing a DFR support film such as polyethylene terepthalate (PET) from the DFR layer on the wafer at a single location. The DFR laminating and PET removing system of the present invention comprises a PET support film removing head for removing a portion of PET film from the semiconductor wafer substrate after the PET film portion and dry film resist (DFR) portion are laminated from a DFR tape onto the wafer and before the DFR portion is cut from the DFR tape.

Abstract: A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CF4, SF4, and H2 and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.

Abstract: A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CF4 and SF6, and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.

Abstract: A DFR laminating and PET removing system which is capable of both laminating a dry film resist (DFR) layer on a semiconductor wafer and removing a DFR support film such as polyethylene terepthalate (PET) from the DFR layer on the wafer at a single location. The DFR laminating and PET removing system of the present invention comprises a PET support film removing head for removing a portion of PET film from the semiconductor wafer substrate after the PET film portion and dry film resist (DFR) portion are laminated from a DFR tape onto the wafer and before the DFR portion is cut from the DFR tape.

Abstract: A stencil design for solder paste printing, or other metal stencil printing, is disclosed. A stencil for stencil printing of solder onto a semiconductor wafer for semiconductor wafer bumping includes a substrate. The substrate has a hole defined therein substantially shaped to correspond to and receptive to the semiconductor wafer. An interior edge of the substrate surrounds the hole, and has an upper lip under which the semiconductor wafer is positioned. The upper lip of the interior edge of the substrate surrounding the hole substantially prevents the solder from flowing onto sides and a bottom of the semiconductor wafer during stencil printing of the solder. The cross-profile shape of the upper lip may in one embodiment be rectangular, whereas in another embodiment be triangular.

Abstract: A Ferris wheel-like stripping or cleaning mechanism that can be used in semiconductor fabrication, such as in photoresist or other stripping, or wafer or other cleaning, is disclosed. A stripping mechanism can include a container to hold a chemical, such as a photoresist stripping chemical, a wafer cleaning chemical, or another type of chemical. The mechanism can also include a component to move semiconductor wafers through the chemical in the container in a Ferris wheel-like motion. The component may include wafer holders for the wafers that are swivably mounted about an axis of rotation. As the one or more wafer holders rotate about the axis of rotation through the chemical in the container, the wafer holders remain in a substantially constant vertical and horizontal orientation.

Abstract: A method including the acts of providing a semiconductor device having a plurality of misalignment ruler markers formed therein for measuring removable layer opening misalignment in the X and Y directions, a bond pad and the passivation layer with an opening therein down to the bond pad. A removable layer is formed over the semiconductor device and includes an opening therein down to the bond pad. Preferably this action includes depositing, patterning and developing a dry photoresist film layer over the semiconductor device with an opening therein down to the bond pad. The next act includes measuring the misalignment of the opening in the passivation layer by counting the number of misalignment ruler markers visibly exposed by the opening in the X-direction and also the Y-direction.

Abstract: A method of fabricating a solder bump including the following steps. A UBM over a substrate.having an exposed pad portion is provided. The UBM being in electrical contact with the pad portion. A first patterning layer is formed over the UBM. The first patterning layer including a photosensitive material sensitive to light having a first wavelength. A second patterning layer is formed over the first patterning layer. The second patterning layer including a photosensitive material sensitive to light having a second wavelength. The first patterning layer is selectively exposed with the light having the first wavelength, leaving a first unexposed portion substantially centered over the pad portion between first exposed portions. The second patterning layer is selectively exposed with the light having the second wavelength, leaving a second unexposed portion wider than, and substantially centered over, the first unexposed portion of the exposed first patterning layer.

Abstract: A method of forming a bump on a substrate such as a semiconductor wafer or flip chip. The method includes the act of providing a semiconductor device having a contact pad and having an upper passivation layer and an opening formed in the upper passivation layer exposing a portion of the contact pad. An under bump metallurgy is deposited over the upper passivation layer and the contact pad. An electrically conductive redistribution trace is deposited over the under bump metallurgy. A photoresist layer is deposited, patterned and developed to provide portions selectively protecting the electrically conductive redistribution trace and the under bump metallurgy. Excess portions of the electrically conductive redistribution trace and under bump metallurgy not protected by the photoresist are removed.

Abstract: A method including the acts of providing a semiconductor device having a plurality of misalignment ruler markers formed therein for measuring removable layer opening misalignment in the X and Y directions, a bond pad and the passivation layer with an opening therein down to the bond pad. A removable layer is formed over the semiconductor device and includes an opening therein down to the bond pad. Preferably this action includes depositing, patterning and developing a dry photoresist film layer over the semiconductor device with an opening therein down to the bond pad. The next act includes measuring the misalignment of the opening in the passivation layer by counting the number of misalignment ruler markers visibly exposed by the opening in the X-direction and also the Y-direction.

Abstract: A method for protecting a semiconductor process wafer surface from contacting thermally degraded photoresist including providing a semiconductor process wafer having a process surface; forming a protective layer over selected areas of the process surface said protective layer including a resinous organic material having a glass transition temperature (Tg) that is about greater than a thermal treatment temperature; forming a photoresist layer over at least a portion of the protective layer to include a photolithographic patterning process; and subjecting the semiconductor process wafer to the thermal treatment temperature.