Abstract: A multi-layered semiconductor structure with free areas limiting the placement of test keys. First and second scribe lines intersect to define one corner point of a die. The first and second scribe lines are part of the multilayered structure and at least one layer of the multi-layer structure is a low-k dielectric layer. Free area A1 is defined on the first scribe line and is defined by the equation A1=D1×S1, where D1 is the distance from the corner point of the die toward the main area of the die, and S1 is the width of the first scribe line. Free area AS is defined at the intersection of the first scribe line and the second scribe line adjacent the die and is defined by the equation AS=S1×S2, where S2 is the width of the second scribe line.

Abstract: A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CF4 and SF6, and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.

Abstract: A multi-layered semiconductor structure with free areas limiting the placement of test keys. First and second scribe lines intersect to define one corner point of a die. The first and second scribe lines are part of the multilayered structure and at least one layer of the multi-layer structure is a low-k dielectric layer. Free area A1 is defined on the first scribe line and is defined by the equation A1=D1×S1, where D1 is the distance from the corner point of the die toward the main area of the die, and S1 is the width of the first scribe line. Free area AS is defined at the intersection of the first scribe line and the second scribe line adjacent the die and is defined by the equation AS=S1×S2, where S2 is the width of the second scribe line.

Abstract: A semiconductor package assembly comprises a first conductive pad on a semiconductor substrate; a second conductive pad on a package substrate; a bump physically coupled between the first conductive pad and the second conductive pad, wherein the bump is substantially lead-free or high-lead-containing; the bump has a first interface with the first conductive pad, the first interface having a first linear dimension; the bump has a second interface with the second conductive pad, the second interface having a second linear dimension; and wherein the ratio of the first linear dimension and the second linear dimension is between about 0.7 and about 1.7.

Abstract: Structures and methods for semiconductor integrated circuits with respect to heat dissipation are provided. The structure comprises a die having a first surface and a second surface. The first surface has an opening in it, and the second surface has a contact pad formed on it. The first surface is opposite to the second surface. A conductive layer is formed over the first surface, covering a surface of the opening.

Abstract: A method and system is disclosed for better packaging semiconductor devices. In one example, a semiconductor device package comprises a package substrate, at least one die with an orientation of <100> placed on the substrate with electrical connections made between the package substrate and the die, and an underfill fillet attaching the die to the substrate with the underfill fillet reaching less than 60% of a thickness of the die on at least one side thereof.

Abstract: A substrate structure comprising a substrate; a solder mask is formed over the substrate; and a metal trace structure formed within the solder mask. The metal trace structure including a channel therein for the receipt of underfill. The metal trace structure further including a central portion with arms radiating outwardly therefrom, dividing the solder mask into separate areas. A method of underfilling a chip wherein a chip having a pattern of solder bumps formed on the underside of the chip is placed underside first onto the metal trace structure of the present invention. The solder bump pattern including openings over the metal trace structure. Underfill is introduced into the metal trace structure so that the underfill flows from the metal trace structure and between the solder bumps to underfill the chip.

Abstract: A new method is provided for the processing of metals, most notably copper, such that damage to exposed surfaces of these metals is prevented. During a step of semiconductor processing, which results in exposing a metal surface to a wet substance having a pH value, a voltage is applied to the metal that is exposed. The value of the applied voltage can, dependent on the value of the pH constant of the wet substance, be selected such that the exposed metal surface is protected against alkaline effects of the wet substance.

Abstract: A method of manufacturing a microelectronic package comprising, in one embodiment, providing a package substrate, coupling a device substrate to the package substrate, and assembling a bifurcated mold around the device and package substrates, the bifurcated mold including a seal. The method also includes encapsulating the device and package substrates employing the bifurcated mold.

Abstract: A method of cutting an integrated circuit chip from a wafer having a plurality of integrated circuit chips is provided. An upper portion of the wafer is ablated using two laser beams to form two substantially parallel trenches that extend into the wafer from a top surface of the wafer through intermetal dielectric layers and at least partially into a substrate of the wafer. After the ablating to form the two trenches, cutting through the wafer between outer sidewalls of the two laser-ablated trenches with a saw blade is performed. A width between the outer sidewalls of the two laser-ablated trenches is greater than a cutting width of the saw blade. This may be particularly useful in lead-free packaging applications and/or applications where the intermetal dielectric layers use low-k dielectric materials, for example.

Abstract: Disclosed are novel spacer structures for stacked semiconductor package devices. In addition, methods of manufacturing spacers and stacked semiconductor package devices having such spacers are also disclosed. In one embodiment, a spacer includes a first mounting surface couplable to a longitudinal face of a first substrate, where the first mounting surface has a first surface area. The spacer also includes a second mounting surface substantially parallel to the first mounting surface and located on an opposing side of the spacer from the first mounting surface. Furthermore, the second mounting surface is couplable to a longitudinal face of a second substrate and has a second surface area larger than the first surface area.

Abstract: A method of bonding a conductive wire on copper pad is presented. A passivation layer is formed on a copper pad. The passivation layer has an opening through which at least a portion of the copper pad is exposed. A nickel-copper-phosphorous (Ni—Cu—P) layer is formed on the copper pad by electroless plating. A conductive wire is bonded through the Ni—Cu—P layer and to the copper pad. The Ni—Cu—P layer protects the underline copper pads from oxidation so that a better bonding can be formed between the conductive wire and the copper pad.

Abstract: A novel integrated circuit (IC) chip package structure and underfill process which reduces stress applied to corners of a flip chip in an IC package structure during the application of an adhesive material between the flip chip and a carrier substrate is disclosed. The process includes providing a dam structure on a carrier substrate; attaching solder bumps of an inverted flip chip to the carrier substrate; injecting an adhesive material between the flip chip and the carrier substrate at multiple injection points located along adjacent edges of the flip chip; and injecting a sealant material around the adhesive material. During application of the adhesive material and the sealant material to the IC package structure in the underfill process, the dam structure reduces stress applied to the corners of the flip chip. This prevents or at least reduces de-lamination of dielectric layers on the flip chip.

Abstract: A substrate structure including a substrate with solder bumps on a main region and a peripheral region of a front side thereof; a solder mask is formed over the front side of the substrate; and a metal trace structure formed within the solder mask. The metal trace structure including a channel therein for the receipt of underfill. The metal trace structure further including a central portion with arms radiating outwardly therefrom, dividing the solder mask into separate areas. A method of underfilling a chip wherein a chip having a pattern of solder bumps formed on the underside of the chip is placed underside first onto the metal trace structure of the present invention. The solder bump pattern includes openings over the metal trace structure. Underfill is introduced into the metal trace structure so that the underfill flows from the metal trace structure and between the solder bumps to underfill the chip.

Abstract: An assembly comprises a substrate, a ring structure bonded to a first side of the substrate; and a die flip-chip-bonded to a second side of the substrate opposite the first side.

Abstract: Structures and methods for semiconductor integrated circuits with respect to heat dissipation are provided. The structure comprises a die having a first surface and a second surface. The first surface has an opening in it, and the second surface has a contact pad formed on it. The first surface is opposite to the second surface. A conductive layer is formed over the first surface, covering a surface of the opening.

Abstract: A method for protecting a semiconductor process wafer surface from contacting thermally degraded photoresist including providing a semiconductor process wafer having a process surface; forming a protective layer over selected areas of the process surface said protective layer including a resinous organic material having a glass transition temperature (Tg) that is about greater than a thermal treatment temperature; forming a photoresist layer over at least a portion of the protective layer to include a photolithographic patterning process; and subjecting the semiconductor process wafer to the thermal treatment temperature.

Abstract: A method of manufacturing a microelectronic package comprising, in one embodiment, providing a package substrate, coupling a device substrate to the package substrate, and assembling a bifurcated mold around the device and package substrates, the bifurcated mold including a seal. The method also includes encapsulating the device and package substrates employing the bifurcated mold.

Abstract: A substrate structure comprising a substrate; a solder mask is formed over the substrate; and a metal trace structure formed within the solder mask. The metal trace structure including a channel therein for the receipt of underfill. The metal trace structure further including a central portion with arms radiating outwardly therefrom, dividing the solder mask into separate areas. A method of underfilling a chip wherein a chip having a pattern of solder bumps formed on the underside of the chip is placed underside first onto the metal trace structure of the present invention. The solder bump pattern including openings over the metal trace structure. Underfill is introduced into the metal trace structure so that the underfill flows from the metal trace structure and between the solder bumps to underfill the chip.

Abstract: A method is disclosed for dicing a wafer having a base material with a diamond structure. The wafer first undergoes a polishing process, in which a predetermined portion of the wafer is polished away from its back side. The wafer is then diced through at least one line along a direction at a predetermined offset angle from a natural cleavage direction of the diamond structure.