Patents by Inventor Hsin-Hung Liao

Hsin-Hung Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10276509
    Abstract: A method for fabricating an integrated fan-out package is provided. The method includes the following steps. A plurality of conductive posts are placed in apertures of a substrate. A carrier having an adhesive thereon is provided. The conductive posts are transferred to the carrier in a standing orientation by adhering the conductive posts in the apertures to the adhesive. An integrated circuit component is mounted onto the adhesive having the conductive posts adhered thereon. An insulating encapsulation is formed to encapsulate the integrated circuit component and the conductive posts. A redistribution circuit structure is formed on the insulating encapsulation, the integrated circuit component, and the conductive posts, wherein the redistribution circuit structure is electrically connected to the integrated circuit component and the conductive posts. The carrier is removed. At least parts of the adhesive are removed (e.g. patterned or entirely removed) to expose surfaces of the conductive posts.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hao Chang, Hsin-Hung Liao, Hao-Yi Tsai, Chien-Ling Hwang, Wei-Sen Chang, Tsung-Hsien Chiang, Tin-Hao Kuo
  • Publication number: 20190123018
    Abstract: A method includes placing a plurality of dummy dies over a carrier, placing a plurality of device dies over the carrier, molding the plurality of dummy dies and the plurality of device dies in a molding compound, forming redistribution line over and electrically coupled to the device dies, and performing a die-saw to separate the device dies and the molding compound into a plurality of packages.
    Type: Application
    Filed: December 17, 2018
    Publication date: April 25, 2019
    Inventors: Chien Ling Hwang, Bor-Ping Jang, Hsin-Hung Liao, Yeong-Jyh Lin, Hsiao-Chung Liang, Chung-Shi Liu
  • Patent number: 10269582
    Abstract: A package structure includes a spiral coil, a redistribution layer (RDL) and a molding material. The molding material fills gaps of the spiral coil. The spiral coil is connected to the RDL. A fan-out package structure includes a spiral coil, an RDL and a die. The spiral coil has a depth-to-width ratio greater than about 2. The RDL is connected to the spiral coil. The die is coupled to the spiral coil through the RDL. A semiconductor packaging method includes: providing a carrier; adhering a spiral coil on the carrier; adhering a die on the carrier; dispensing a molding material on the carrier to fill gaps between the spiral coil and the die; and disposing a redistribution layer (RDL) over the carrier so as to connect the spiral coil with the die.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chien Ling Hwang, Hsin-Hung Liao, Yu-Ting Chiu
  • Publication number: 20190074259
    Abstract: A conductive micro pin includes a body having a first end surface, a second end surface, a first side surface connecting the first end surface and the second end surface, and a first corner between the first end surface and the first side surface, in which the first side surface is substantially flat, and the first corner is substantially rounded.
    Type: Application
    Filed: October 29, 2018
    Publication date: March 7, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ying-Jui HUANG, Chung-Shi LIU, Hsin-Hung LIAO, Chien-Ling HWANG
  • Patent number: 10157881
    Abstract: A method includes placing a plurality of dummy dies over a carrier, placing a plurality of device dies over the carrier, molding the plurality of dummy dies and the plurality of device dies in a molding compound, forming redistribution line over and electrically coupled to the device dies, and performing a die-saw to separate the device dies and the molding compound into a plurality of packages.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Bor-Ping Jang, Hsin-Hung Liao, Yeong-Jyh Lin, Hsiao-Chung Liang, Chung-Shi Liu
  • Publication number: 20180358255
    Abstract: A semiconductor device includes a carrier having a first central axis extending along a first direction and a second central axis extending along a second direction, a plurality of dies disposed on a surface of the carrier, and a plurality of scribing lines separating the plurality of dies from each other. The plurality of scribing lines include a plurality of continuous lines along the first direction and a plurality of discontinuous lines along the second direction, at least one of the plurality of continuous lines overlaps the first central axis, at least one of the plurality of discontinuous lines overlaps the second central axis. The plurality of dies are symmetrically arranged on the carrier about the first central axis and the second central axis.
    Type: Application
    Filed: August 20, 2018
    Publication date: December 13, 2018
    Inventors: BOR-PING JANG, CHIEN LING HWANG, HSIN-HUNG LIAO, YEONG-JYH LIN
  • Patent number: 10115690
    Abstract: A method of manufacturing micro pins includes forming a release layer over a substrate. A pattern layer is formed over the release layer, in which the pattern layer has a plurality of openings spaced apart to each other and through the pattern layer. A plurality of micro pins are respectively formed in the openings. The pattern layer and the release layer are removed to obtain the micro pins. An isolated conductive micro pin for connecting one or more components is also provided.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: October 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ying-Jui Huang, Chung-Shi Liu, Hsin-Hung Liao, Chien-Ling Hwang
  • Patent number: 10056285
    Abstract: A method of dies singulation includes providing a carrier, disposing a plurality of dies over a surface of the carrier according to a plurality of scribe lines comprising a plurality of continuous lines along a first direction and a plurality of discontinuous lines along a second direction, cutting the carrier according to the plurality of continuous lines along the first direction, and cutting the carrier according to the plurality of discontinuous lines along the second direction.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: August 21, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Bor-Ping Jang, Chien Ling Hwang, Hsin-Hung Liao, Yeong-Jyh Lin
  • Patent number: 9984960
    Abstract: Provided is an integrated fan-out package including a die, a first redistribution circuit structure, a second redistribution circuit structure, a plurality of solder joints, a plurality of conductive posts, and an insulating encapsulation. The first redistribution circuit structure and the second redistribution circuit structure are formed respectively over a back surface and an active surface of the die to sandwich the die. The solder joints are formed aside the die and connected to the first redistribution circuit structure. The conductive posts are formed on the solder joints and connected to the second redistribution circuit structure, and connected to the first redistribution circuit structure through the solder joints. A plurality of sidewalls of the die, a plurality of sidewalls of the conductive posts, and a plurality of sidewalls of the solder joints are encapsulated by the insulating encapsulation. A fabricating process of the integrated fan-out package is also provided.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: May 29, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Ling Hwang, Ching-Hua Hsieh, Hsin-Hung Liao, Ying-Jui Huang
  • Publication number: 20180130673
    Abstract: A package structure includes a spiral coil, a redistribution layer (RDL) and a molding material. The molding material fills gaps of the spiral coil. The spiral coil is connected to the RDL. A fan-out package structure includes a spiral coil, an RDL and a die. The spiral coil has a depth-to-width ratio greater than about 2. The RDL is connected to the spiral coil. The die is coupled to the spiral coil through the RDL. A semiconductor packaging method includes: providing a carrier; adhering a spiral coil on the carrier; adhering a die on the carrier; dispensing a molding material on the carrier to fill gaps between the spiral coil and the die; and disposing a redistribution layer (RDL) over the carrier so as to connect the spiral coil with the die.
    Type: Application
    Filed: January 3, 2018
    Publication date: May 10, 2018
    Inventors: CHIEN LING HWANG, HSIN-HUNG LIAO, YU-TING CHIU
  • Publication number: 20180090445
    Abstract: A method for fabricating an integrated fan-out package is provided. The method includes the following steps. A plurality of conductive posts are placed in apertures of a substrate. A carrier having an adhesive thereon is provided. The conductive posts are transferred to the carrier in a standing orientation by adhering the conductive posts in the apertures to the adhesive. An integrated circuit component is mounted onto the adhesive having the conductive posts adhered thereon. An insulating encapsulation is formed to encapsulate the integrated circuit component and the conductive posts. A redistribution circuit structure is formed on the insulating encapsulation, the integrated circuit component, and the conductive posts, wherein the redistribution circuit structure is electrically connected to the integrated circuit component and the conductive posts. The carrier is removed. At least parts of the adhesive are removed (e.g. patterned or entirely removed) to expose surfaces of the conductive posts.
    Type: Application
    Filed: November 30, 2017
    Publication date: March 29, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hao Chang, Hsin-Hung Liao, Hao-Yi Tsai, Chien-Ling Hwang, Wei-Sen Chang, Tsung-Hsien Chiang, Tin-Hao Kuo
  • Publication number: 20180047611
    Abstract: A method of dies singulation includes providing a carrier, disposing a plurality of dies over a surface of the carrier according to a plurality of scribe lines comprising a plurality of continuous lines along a first direction and a plurality of discontinuous lines along a second direction, cutting the carrier according to the plurality of continuous lines along the first direction, and cutting the carrier according to the plurality of discontinuous lines along the second direction.
    Type: Application
    Filed: October 23, 2017
    Publication date: February 15, 2018
    Inventors: BOR-PING JANG, CHIEN LING HWANG, HSIN-HUNG LIAO, YEONG-JYH LIN
  • Publication number: 20180025966
    Abstract: Provided is an integrated fan-out package including a die, a first redistribution circuit structure, a second redistribution circuit structure, a plurality of solder joints, a plurality of conductive posts, and an insulating encapsulation. The first redistribution circuit structure and the second redistribution circuit structure are formed respectively over a back surface and an active surface of the die to sandwich the die. The solder joints are formed aside the die and connected to the first redistribution circuit structure. The conductive posts are formed on the solder joints and connected to the second redistribution circuit structure, and connected to the first redistribution circuit structure through the solder joints. A plurality of sidewalls of the die, a plurality of sidewalls of the conductive posts, and a plurality of sidewalls of the solder joints are encapsulated by the insulating encapsulation. A fabricating process of the integrated fan-out package is also provided.
    Type: Application
    Filed: July 21, 2016
    Publication date: January 25, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Ling Hwang, Ching-Hua Hsieh, Hsin-Hung Liao, Ying-Jui Huang
  • Patent number: 9870997
    Abstract: A method for fabricating an integrated fan-out package is provided. The method includes the following steps. A plurality of conductive posts are placed in apertures of a substrate. A carrier having an adhesive thereon is provided. The conductive posts are transferred to the carrier in a standing orientation by adhering the conductive posts in the apertures to the adhesive. An integrated circuit component is mounted onto the adhesive having the conductive posts adhered thereon. An insulating encapsulation is formed to encapsulate the integrated circuit component and the conductive posts. A redistribution circuit structure is formed on the insulating encapsulation, the integrated circuit component, and the conductive posts, wherein the redistribution circuit structure is electrically connected to the integrated circuit component and the conductive posts. The carrier is removed. At least parts of the adhesive are removed (e.g. patterned or entirely removed) to expose surfaces of the conductive posts.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hao Chang, Hsin-Hung Liao, Hao-Yi Tsai, Chien-Ling Hwang, Wei-Sen Chang, Tsung-Hsien Chiang, Tin-Hao Kuo
  • Patent number: 9870929
    Abstract: A package structure includes a spiral coil, a redistribution layer (RDL) and a molding material. The molding material fills gaps of the spiral coil. The spiral coil is connected to the RDL. A fan-out package structure includes a spiral coil, an RDL and a die. The spiral coil has a depth-to-width ratio greater than about 2. The RDL is connected to the spiral coil. The die is coupled to the spiral coil through the RDL. A semiconductor packaging method includes: providing a carrier; adhering a spiral coil on the carrier; adhering a die on the carrier; dispensing a molding material on the carrier to fill gaps between the spiral coil and the die; and disposing a redistribution layer (RDL) over the carrier so as to connect the spiral coil with the die.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: January 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chien Ling Hwang, Hsin-Hung Liao, Yu-Ting Chiu
  • Publication number: 20180005976
    Abstract: Embodiments of mechanisms for forming a package are provided. The package includes a substrate and a contact pad formed on the substrate. The package also includes a conductive pillar bonded to the contact pad through solder formed between the conductive pillar and the contact pad. The solder is in direct contact with the conductive pillar.
    Type: Application
    Filed: September 18, 2017
    Publication date: January 4, 2018
    Inventors: Yeong-Jyh Lin, Hsin-Hung Liao, Chien Ling Hwang, Bor-Ping Jang, Hsiao-Chung Liang, Chung-Shi Liu
  • Publication number: 20170352641
    Abstract: A method for mounting components on a substrate is provided. The method includes providing a positioning plate which has a plurality of through holes. The method further includes supplying components each having a longitudinal portion on the positioning plate. The method also includes performing a component alignment process to put the longitudinal portions of the components in the through holes. In addition, the method includes connecting a substrate to the components which have their longitudinal portions in the through holes and removing the positioning plate.
    Type: Application
    Filed: June 6, 2016
    Publication date: December 7, 2017
    Inventors: Chien-Ling HWANG, Hsin-Hung LIAO, Yu-Ting CHIU, Ching-Hua HSIEH
  • Publication number: 20170345764
    Abstract: A method for fabricating an integrated fan-out package is provided. The method includes the following steps. A plurality of conductive posts are placed in apertures of a substrate. A carrier having an adhesive thereon is provided. The conductive posts are transferred to the carrier in a standing orientation by adhering the conductive posts in the apertures to the adhesive. An integrated circuit component is mounted onto the adhesive having the conductive posts adhered thereon. An insulating encapsulation is formed to encapsulate the integrated circuit component and the conductive posts. A redistribution circuit structure is formed on the insulating encapsulation, the integrated circuit component, and the conductive posts, wherein the redistribution circuit structure is electrically connected to the integrated circuit component and the conductive posts. The carrier is removed. At least parts of the adhesive are removed (e.g. patterned or entirely removed) to expose surfaces of the conductive posts.
    Type: Application
    Filed: September 20, 2016
    Publication date: November 30, 2017
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hao Chang, Hsin-Hung Liao, Hao-Yi Tsai, Chien-Ling Hwang, Wei-Sen Chang, Tsung-Hsien Chiang, Tin-Hao Kuo
  • Patent number: 9812346
    Abstract: A method of manufacturing a semiconductor device comprises providing a carrier, disposing a plurality of dies over the carrier along a first direction and a second direction orthogonal to the first direction to arrange the plurality of dies in a plurality of rows, and shifting one of the plurality of rows along the first direction or the second direction in a predetermined distance.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: November 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Bor-Ping Jang, Chien Ling Hwang, Hsin-Hung Liao, Yeong-Jyh Lin
  • Patent number: 9768142
    Abstract: Embodiments of mechanisms for forming a package are provided. The package includes a substrate and a contact pad formed on the substrate. The package also includes a conductive pillar bonded to the contact pad through solder formed between the conductive pillar and the contact pad. The solder is in direct contact with the conductive pillar.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yeong-Jyh Lin, Hsin-Hung Liao, Chien Ling Hwang, Bor-Ping Jang, Hsiao-Chung Liang, Chung-Shi Liu