Patents by Inventor Hsin Lu

Hsin Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220352021
    Abstract: An apparatus for electroplating includes a cup configured to support a substrate, and a cone including at least three distance measuring devices arranged on a lower surface thereof and facing the substrate. Each distance measuring device is configured to transmit a laser pulse towards the substrate, the laser pulse impinging the substrate, receive a reflected laser pulse from the substrate, calculate a turnaround time of the laser pulse, and calculate a distance between the distance measuring device and the substrate using the turnaround time for determining an inclination of the substrate.
    Type: Application
    Filed: July 14, 2022
    Publication date: November 3, 2022
    Inventors: Kuo-Lung HOU, Ming-Hsien LIN, Che-I KUO, Yung Hsin LU
  • Publication number: 20220336272
    Abstract: An apparatus for electroplating includes a cup configured to support a substrate, and a cone including at least three distance measuring devices arranged on a lower surface thereof and facing the substrate. Each distance measuring device is configured to transmit a laser pulse towards the substrate, the laser pulse impinging the substrate, receive a reflected laser pulse from the substrate, calculate a turnaround time of the laser pulse, and calculate a distance between the distance measuring device and the substrate using the turnaround time for determining an inclination of the substrate.
    Type: Application
    Filed: April 15, 2021
    Publication date: October 20, 2022
    Inventors: Kuo-Lung HOU, Ming-Hsien LIN, Che-I KUO, Yung Hsin LU
  • Patent number: 11476351
    Abstract: A method includes forming a dummy gate stack over a fin protruding from a semiconductor substrate, forming gate spacers on sidewalls of the dummy gate stack, forming source/features over portions of the fin, forming a gate trench between the gate spacers, which includes trimming top portions of the gate spacers to form a funnel-like opening in the gate trench, and forming a metal gate structure in the gate trench. A semiconductor structure includes a fin protruding from a substrate, a metal gate structure disposed over the fin, gate spacers disposed on sidewalls of the metal gate structure, where a top surface of each gate spacer is angled toward the semiconductor fin, a dielectric layer disposed over the top surface of each gate spacer, and a conductive feature disposed between the gate spacers to contact the metal gate structure, where sidewalls of the conductive feature contact the dielectric layer.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: October 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ru-Shang Hsiao, Ching-Hwanq Su, Pin Chia Su, Ying Hsin Lu, I-Shan Huang
  • Patent number: 11471034
    Abstract: A method for distinguishing plaque and calculus is provided. The method is used in a device and includes the following steps: emitting, by a blue light-emitting diode, blue light to illuminate teeth in an oral cavity, wherein the blue light is used to generate autofluorescence of plaque and calculus on the teeth; sensing, by an image sensor, the autofluorescence of plaque and calculus; and distinguishing, by a processor, a plaque area and a calculus area on the teeth based on the autofluorescence.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: October 18, 2022
    Assignee: QUANTA COMPUTER INC.
    Inventors: Kai-Ju Cheng, Hsin-Lun Hsieh, Chin-Yuan Ting, Tsung-Hsin Lu, Huan-Tang Wu, Shao-Ang Chen, Yu-Hsun Chen, Jia-Chyi Wang, Chih-Wei Sung, Huan-Pin Shen
  • Patent number: 11450758
    Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a fin extending from a substrate. A sacrificial gate electrode layer is formed along a sidewall and a top surface of the fin. A patterning process is performed on the sacrificial gate electrode layer to form a sacrificial gate electrode. A reshaping process is performed on the sacrificial gate electrode to form a reshaped sacrificial gate electrode. The reshaped sacrificial gate electrode includes a first portion along the top surface of the fin and a second portion along the sidewall of the fin. A width of the first portion decreases as the first portion extends from a top surface of the first portion toward the top surface of the fin. A width of the second portion decreases as the second portion extends from the top surface of the fin toward the substrate.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ru-Shang Hsiao, Ying Ming Wang, Ying Hsin Lu
  • Patent number: 11444634
    Abstract: A time-interleaved noise-shaping successive-approximation analog-to-digital converter (TI NS-SAR ADC) is shown. A first successive-approximation channel has a first set of successive-approximation registers, and a first coarse comparator operative to coarsely adjust the first set of successive-approximation registers. A second successive-approximation channel has a second set of successive-approximation registers, and a second coarse comparator operative to coarsely adjust the second set of successive-approximation registers. A fine comparator is provided to finely adjust the first set of successive-approximation registers and the second set of successive-approximation registers alternately. A noise-shaping circuit is provided to sample residues of the first and second successive-approximation channels for the fine comparator to finely adjust the first and second sets of successive-approximation registers.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: September 13, 2022
    Assignee: MEDIATEK INC.
    Inventors: Chin-Yu Lin, Ying-Zu Lin, Chih-Hou Tsai, Chao-Hsin Lu
  • Publication number: 20220252967
    Abstract: An illumination system for providing an illumination beam includes red, blue, and green light source modules, a first light combining element, and a light uniforming element. The red light source module includes a first red light emitting element emitting first red light and a second red light emitting element emitting second red light. A peak wavelength of the second red light is greater than a peak wavelength of the first red light. The blue light source module includes a first blue light emitting element emitting first blue light and a second blue light emitting element emitting second blue light. A peak wavelength of the second blue light is less than a peak wavelength of the first blue light. The green light source module generates green light. The first light combining element guides these lights into the light uniforming element, so that the illumination system outputs the illumination beam.
    Type: Application
    Filed: January 18, 2022
    Publication date: August 11, 2022
    Applicant: Coretronic Corporation
    Inventors: Hung-Yu Lin, Chi-Fu Liu, Chun-Hsin Lu, Chun-Li Chen
  • Patent number: 11405597
    Abstract: An illumination system and a projection device are provided. The illumination system includes an excitation light source, a wavelength conversion module and a light combining prism. The excitation light source emits an exciting light beam. The light combining prism has a first, second, and third surfaces. The exciting light beam enters the light combining prism through the first surface, and is totally reflected by the second surface to leave the light combining prism through the third surface and is transmitted to the wavelength conversion module. The exciting light beam is converted into a wavelength converted light beam by a wavelength conversion region of the wavelength conversion module or reflected by a reflecting region of the wavelength conversion module at different timings, and the wavelength converted light beam or the exciting light beam sequentially penetrates through the third surface and the second surface to leave the light combining prism.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: August 2, 2022
    Assignee: Coretronic Corporation
    Inventors: Chun-Li Chen, Kun-Liang Jao, Chun-Hsin Lu
  • Publication number: 20220223590
    Abstract: An embodiment includes a semiconductor device, a plurality of fin structures extending from a substrate, the plurality of fin structures having a plurality of first fin structures and a plurality of second fin structures. The semiconductor device also includes a plurality of isolation regions on the substrate and disposed between the plurality of fin structures. The device also includes a plurality of gate structures on the plurality of isolation regions. The device also includes a plurality of epitaxy structures on one of the plurality of first fin structures. The device also includes a plurality of contact structures on the plurality of epitaxy structures, where the plurality of first fin structures, the plurality of gate structures, the plurality of epitaxy structures, and the plurality of contact structures are components of one or more resonators.
    Type: Application
    Filed: November 23, 2021
    Publication date: July 14, 2022
    Inventors: Hsi-Jung WU, Sheng-Fu YU, Ru-Shang Hsiao, Ying-Hsin Lu
  • Publication number: 20220216317
    Abstract: A semiconductor device includes a channel component of a transistor and a gate component disposed over the channel component. The gate component includes: a dielectric layer, a first work function metal layer disposed over the dielectric layer, a fill-metal layer disposed over the first work function metal layer, and a second work function metal layer disposed over the fill-metal layer.
    Type: Application
    Filed: March 21, 2022
    Publication date: July 7, 2022
    Inventors: Ru-Shang Hsiao, Ching-Hwanq Su, Pohan Kung, Ying Hsin Lu, I-Shan Huang
  • Patent number: 11342417
    Abstract: A structure of trench transistors includes the following elements. A substrate serves as a drain of the structure of trench transistors. An epitaxial layer is disposed on the substrate. A plurality of trenches are disposed in the epitaxial layer. A plurality of gate insulator layers are respectively disposed on the inner surfaces of the trenches. A plurality of gates are respectively disposed on the gate insulator layers. A plurality of first base regions are respectively disposed in the epitaxial layer between the adjacent trenches, and have a first depth from the top surface of the epitaxial layer. A plurality of second base regions are respectively disposed in the epitaxial layer adjacent to the sidewalls of the trenches, and each has a second depth from the bottom surface of the first base region. A plurality of sources are respectively disposed in the first base region beside the sidewalls of the trenches.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: May 24, 2022
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Bing-Yue Tsui, Fang-Hsin Lu
  • Publication number: 20220148923
    Abstract: A method for increasing an oxide thickness at trench corner of an UMOSFET is provided, comprising providing an N-type substrate, and forming an N-type drift region, N-type and P-type heavily doped regions and P-type body therein. A trench is defined through lithography, and a pad oxide is formed along the trench through oxidation or deposition process. An oxidation barrier is formed upon the pad oxide. A thermal oxidation process is employed, so a corner oxide is effectively formed at the trench corner. After removing the pad oxide and oxidation barrier, various back-end processes are carried out to complete the transistor structure. The invention is aimed to increase oxide thickness near the trench bottom, and can be applied to high voltage devices, such as SiC.
    Type: Application
    Filed: January 29, 2021
    Publication date: May 12, 2022
    Applicant: National Chiao Tung University
    Inventors: Bing-Yue Tsui, Fang-Hsin Lu, Yi-Ting Shih
  • Patent number: 11282934
    Abstract: A semiconductor device includes a channel component of a transistor and a gate component disposed over the channel component. The gate component includes: a dielectric layer, a first work function metal layer disposed over the dielectric layer, a fill-metal layer disposed over the first work function metal layer, and a second work function metal layer disposed over the fill-metal layer.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ru-Shang Hsiao, Ching-Hwanq Su, Pohan Kung, Ying Hsin Lu, I-Shan Huang
  • Publication number: 20220057681
    Abstract: A display panel and a display device are provided. The display panel has a first region and a second region. A finger structure of a pixel unit located in the first region has one extending direction, and a finger structure of a pixel unit located in the second region has at least one extending direction. In particular, a size of the pixel unit in the first region is larger than a size of the pixel unit in the second region.
    Type: Application
    Filed: July 21, 2021
    Publication date: February 24, 2022
    Applicant: Innolux Corporation
    Inventors: Chia-Hao Tsai, Yu-Shih Tsou, Yung-Hsun Wu, Jian-Min Leu, Ming-Jou Tai, En Jie Chen, Yung-Hsin Lu
  • Publication number: 20220025549
    Abstract: A silicon carbide wafer and a method of fabricating the same are provided. In the silicon carbide wafer, a ratio (V:N) of a vanadium concentration to a nitrogen concentration is in a range of 2:1 to 10:1, and a portion of the silicon carbide wafer having a resistivity greater than 1012 ?·cm accounts for more than 85% of an entire wafer area of the silicon carbide wafer.
    Type: Application
    Filed: July 27, 2021
    Publication date: January 27, 2022
    Applicant: GlobalWafers Co., Ltd.
    Inventors: Ching-Shan Lin, Chien-Cheng Liou, Jian-Hsin Lu
  • Patent number: 11227421
    Abstract: A method of constructing a map including a plurality of lanes and a system thereof are provided. The method includes: for each of the plurality of lanes, constructing corresponding lane geometry data based on a plurality of polyline segments, including constructing a general outline circumscribing the plurality of lanes and identifying an outline of each of the plurality of lanes based on the plurality of polyline segments and the general outline. Outline polyline segments as boundaries of the general outline are selected from the plurality of polyline segments.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: January 18, 2022
    Assignee: TUSIMPLE, INC.
    Inventors: Minhao Jiang, Hsin Lu, Genmao Shi, Ziqi Liu
  • Publication number: 20210404839
    Abstract: Systems and methods for navigational map version management are disclosed. In one aspect, a map management server includes a processor and a computer-readable memory having stored thereon a navigational map including a plurality of units, each of the units covering an area and including a plurality of objects within or adjacent to roadways within the area. The processor is configured to receive update data for the navigational map, the update data including object data to update the navigational map. The processor is also configured to create a released version of the navigational map that includes one or more updated units. The processor is further configured to provide the released version of the navigational map to an autonomous vehicle.
    Type: Application
    Filed: June 30, 2020
    Publication date: December 30, 2021
    Inventors: Minhao Jiang, Genmao Shi, Hsin Lu, Ziqi Liu
  • Publication number: 20210405647
    Abstract: Systems and methods for projecting a three-dimensional (3D) surface to a two-dimensional (2D) surface for use in autonomous driving are disclosed. In one aspect, a control system for an autonomous vehicle includes a processor and a computer-readable memory in communication with the processor and having stored thereon computer-executable instructions to cause the processor to: receive a 3D map including a plurality of objects, determine a base point in the 3D map, shift the objects in the 3D map based on the base point, project the objects in the shifted 3D map to a 2D map, and output the 2D map.
    Type: Application
    Filed: June 30, 2020
    Publication date: December 30, 2021
    Inventors: Minhao Jiang, Genmao Shi, Hsin Lu, Ziqi Liu
  • Publication number: 20210391441
    Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a fin extending from a substrate. A sacrificial gate electrode layer is formed along a sidewall and a top surface of the fin. A patterning process is performed on the sacrificial gate electrode layer to form a sacrificial gate electrode. A reshaping process is performed on the sacrificial gate electrode to form a reshaped sacrificial gate electrode. The reshaped sacrificial gate electrode includes a first portion along the top surface of the fin and a second portion along the sidewall of the fin. A width of the first portion decreases as the first portion extends from a top surface of the first portion toward the top surface of the fin. A width of the second portion decreases as the second portion extends from the top surface of the fin toward the substrate.
    Type: Application
    Filed: June 12, 2020
    Publication date: December 16, 2021
    Inventors: Ru-Shang Hsiao, Ying Ming Wang, Ying Hsin Lu
  • Publication number: 20210383137
    Abstract: A method of retrieving a map is disclosed. The method includes receiving a grid data of the map comprising lane segments, wherein the grid data includes an array of grids each associated with a list including none or at least one of the lane segments intersecting the respective grid; receiving coordinates of a location; identifying a first grid including the location based on the grid data; identifying a target grid that has an associated list including at least one of the lane segments as first lane segment; and outputting the first lane segment.
    Type: Application
    Filed: August 18, 2021
    Publication date: December 9, 2021
    Inventors: Minhao JIANG, Hsin LU, Genmao SHI, Ziqi LIU