Patents by Inventor Hsin Lu

Hsin Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250146832
    Abstract: Disclosed are devices, systems and methods for displaying a map for a user. A method of displaying a map for a user comprises: receiving, from a user device, a request to display the map for a geographical region around a vehicle, wherein the request identifies one or more layers of the map; retrieving, in response to the request, map data corresponding to the geographical region from a map database that stores a multi-layer representation of the geographical region; selecting, in response to the request, the one or more layers from the multi-layer representation; and displaying the map on a display of the user device based on the request.
    Type: Application
    Filed: October 31, 2024
    Publication date: May 8, 2025
    Inventors: Ruimin ZENG, Anying ZHENG, Wan-Ting HUNG, Anpin WANG, Minhao JIANG, Hsin LU
  • Publication number: 20250139855
    Abstract: A computer-implemented method of map data processing, comprising generating, for a grid-based representation of map data, raw grid features; building a grid map by reading from a memory that stores the raw grid features; and processing the grid map using one or more post-processing operations including a smoothing operation applied across zero or more grid lines of the grid map according to a rule.
    Type: Application
    Filed: October 29, 2024
    Publication date: May 1, 2025
    Inventors: Ke XU, Thomas Datong WANG, Hsin LU, Bolun ZHANG, Adan Daniel ARTEAGA ORGANIZ, Shicong MA, Tu Thanh TRAN, Shenchao ZHANG, Jinjian ZHAI, Wan-Ting HUNG, Anping WANG
  • Publication number: 20250081255
    Abstract: The present disclosure discloses a Bluetooth communication system. A first access point apparatus of a Bluetooth access point apparatus performs periodic broadcast communication.
    Type: Application
    Filed: August 29, 2024
    Publication date: March 6, 2025
    Inventors: CHIA-CHUN HUNG, Li-Ya Huang, Hsin-Yu Chang, Yu Chiang, Po-Sheng Chiu, Yu-Hsin Lu
  • Patent number: 12237220
    Abstract: An apparatus for electroplating includes a cup configured to support a substrate, and a cone including at least three distance measuring devices arranged on a lower surface thereof and facing the substrate. Each distance measuring device is configured to transmit a laser pulse towards the substrate, the laser pulse impinging the substrate, receive a reflected laser pulse from the substrate, calculate a turnaround time of the laser pulse, and calculate a distance between the distance measuring device and the substrate using the turnaround time for determining an inclination of the substrate.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Lung Hou, Ming-Hsien Lin, Che-I Kuo, Yung Hsin Lu
  • Patent number: 12190609
    Abstract: A method of retrieving a map includes receiving a grid data of the map comprising lane segments, wherein the grid data includes an array of grids each associated with a list including none or at least one of the lane segments intersecting the respective grid; receiving coordinates of a location; identifying a first grid including the location based on the grid data; identifying a target grid that has an associated list including at least one of the lane segments as first lane segment; and outputting the first lane segment.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: January 7, 2025
    Assignee: TUSIMPLE, INC.
    Inventors: Minhao Jiang, Hsin Lu, Genmao Shi, Ziqi Liu
  • Publication number: 20250004148
    Abstract: Disclosed is a pixel sensor circuit including a photodiode element and a transistor element. The photodiode element is configured to sense an X-ray to generate a photocurrent signal. The photodiode element has a first end and a second end. A bias voltage is applied to the first end of the photodiode element. The transistor element is coupled to the second end of the photodiode element. The transistor element is configured to control the photocurrent signal to be read out. The voltage value of the bias voltage is adjusted according to the intensity of the X-ray.
    Type: Application
    Filed: May 14, 2024
    Publication date: January 2, 2025
    Applicant: InnoCare Optoelectronics Corporation
    Inventors: Hui-Hsin Lu, Zong-Yi Hsiao, Jheng-You Lin, Hsin-Han Shen
  • Patent number: 12164304
    Abstract: Systems and methods for projecting a three-dimensional (3D) surface to a two-dimensional (2D) surface for use in autonomous driving are disclosed. In one aspect, a control system for an autonomous vehicle includes a processor and a computer-readable memory in communication with the processor and having stored thereon computer-executable instructions to cause the processor to: receive a 3D map including a plurality of objects, determine a base point in the 3D map, shift the objects in the 3D map based on the base point, project the objects in the shifted 3D map to a 2D map, and output the 2D map.
    Type: Grant
    Filed: March 24, 2023
    Date of Patent: December 10, 2024
    Assignee: TUSIMPLE, INC.
    Inventors: Minhao Jiang, Genmao Shi, Hsin Lu, Ziqi Liu
  • Publication number: 20240401235
    Abstract: A silicon carbide wafer and a method of fabricating the same are provided. In the silicon carbide wafer, a ratio (V:N) of a vanadium concentration to a nitrogen concentration is in a range of 2:1 to 10:1, and a portion of the silicon carbide wafer having a resistivity greater than 1012 ?·cm accounts for more than 85% of an entire wafer area of the silicon carbide wafer.
    Type: Application
    Filed: August 12, 2024
    Publication date: December 5, 2024
    Applicant: GlobalWafers Co., Ltd.
    Inventors: Ching-Shan Lin, Chien-Cheng Liou, Jian-Hsin Lu
  • Publication number: 20240393653
    Abstract: A package structure and method for forming the same are provided. The package structure includes a substrate having a front-side surface and a back-side surface, and an electrical device formed over the front-side surface of a substrate. The package structure includes a dielectric layer formed below and in direct contact with the back-side surface of the substrate, and a first optical device formed in the dielectric layer. The package structure also includes a protective layer formed below or above the first optical device; and an electro-optic effect material layer formed in the protective layer.
    Type: Application
    Filed: May 25, 2023
    Publication date: November 28, 2024
    Inventors: Chih-Hsin LU, Chia-Chia LIN, Ching-Ho CHIN, Chung-Hao TSAI, Chuei-Tang WANG, Chen-Hua YU
  • Publication number: 20240387489
    Abstract: A package structure is provided, and includes an interposer, a control unit, a plurality of computing units, a signal transmission layer, and an electric-optical material. The control unit is bonded to the interposer. The computing units are disposed around and connected to the control unit. The signal transmission layer is formed in the control unit and the computing units. The electric-optical material is formed in the control unit and the computing units, and the electric-optical material overlaps the signal transmission layer.
    Type: Application
    Filed: May 16, 2023
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chia LIN, Chih-Hsin LU, Chung-Hao TSAI, Hsing-Kuo HSIA, Chuei-Tang WANG, Chen-Hua YU
  • Publication number: 20240387536
    Abstract: An embodiment includes a semiconductor device, a plurality of fin structures extending from a substrate, the plurality of fin structures having a plurality of first fin structures and a plurality of second fin structures. The semiconductor device also includes a plurality of isolation regions on the substrate and disposed between the plurality of fin structures. The device also includes a plurality of gate structures on the plurality of isolation regions. The device also includes a plurality of epitaxy structures on one of the plurality of first fin structures. The device also includes a plurality of contact structures on the plurality of epitaxy structures, where the plurality of first fin structures, the plurality of gate structures, the plurality of epitaxy structures, and the plurality of contact structures are components of one or more resonators.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Hsi-Jung Wu, Sheng-Fu Yu, Ru-Shang Hsiao, Ying-Hsin Lu
  • Publication number: 20240387329
    Abstract: A package structure and a formation method are provided. The method includes forming electrical devices over a substrate and forming an interconnect structure over front sides of the electrical devices. The method also includes thinning the substrate and forming backside through vias connecting to backsides of the electrical devices. The method also includes attaching a waveguide layer over backsides of the electrical devices and forming conductive vias through the waveguide layer and electrically connected to the backside through vias.
    Type: Application
    Filed: May 19, 2023
    Publication date: November 21, 2024
    Inventors: Chih-Hsin LU, Chia-Chia LIN, Ching-Ho CHIN, Chung-Hao TSAI, Chuei-Tang WANG, Chen-Hua YU
  • Publication number: 20240363734
    Abstract: A method includes forming a dummy gate stack over a semiconductor region, removing the dummy gate stack to form a trench between gate spacers, forming a replacement gate dielectric extending into the trench, and forming a replacement gate electrode on the replacement gate dielectric. The forming the replacement gate electrode includes depositing a metal-containing layer. The depositing the metal-containing layer includes depositing a lower layer having a first average grain size, and depositing an upper layer over the lower layer. The lower layer and the upper layer are formed of a same material, and the upper layer has a second average grain size greater than the first average grain size. Source and drain regions are formed on opposing sides of the replacement gate electrode.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Inventors: Ru-Shang Hsiao, Ching-Hwanq Su, Pin Chia Su, Ying Hsin Lu, Ling-Sung Wang
  • Publication number: 20240361521
    Abstract: A photonic integrated circuit (PIC) with a first structure of a ordinary optical material is enhanced with a second structure of a nonlinear optical material. The second structure provides or enhances nonlinear optical effects within the PIC. The first structure and the second structure may be in distinct layers. The first structure may be directly over and in contact with the second structure. Alternatively, the first structure and the second structures may be evanescently coupled while being vertically separated by a layer of cladding material. Lateral spacing may be used in combination with vertically spacing to precisely control a degree coupling between the first structure and the second structure.
    Type: Application
    Filed: April 28, 2023
    Publication date: October 31, 2024
    Inventors: Chih-Hsin Lu, Chia-Chia Lin, Chung-Hao Tsai, Chuei-Tang Wang, Chen-Hua Yu
  • Publication number: 20240363406
    Abstract: An apparatus for electroplating includes a cup configured to support a substrate, and a cone including at least three distance measuring devices arranged on a lower surface thereof and facing the substrate. Each distance measuring device is configured to transmit a laser pulse towards the substrate, the laser pulse impinging the substrate, receive a reflected laser pulse from the substrate, calculate a turnaround time of the laser pulse, and calculate a distance between the distance measuring device and the substrate using the turnaround time for determining an inclination of the substrate.
    Type: Application
    Filed: July 12, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Lung HOU, Ming-Hsien LIN, Che-I KUO, Yung Hsin LU
  • Publication number: 20240345305
    Abstract: A head mounted electronic device includes a dimming module. The dimming module has a normal direction. The dimming module has a first transmittance T1 in the normal direction and a second transmittance T2 in an oblique direction. An included angle between the oblique direction and the normal direction is 60 degrees. The head mounted electronic device satisfies: [(T1-T2)/T1]*100%<50%.
    Type: Application
    Filed: March 7, 2024
    Publication date: October 17, 2024
    Applicant: Innolux Corporation
    Inventors: Jian-Min Leu, Chih-Lung Lin, Yung-Hsin Lu
  • Patent number: D1061464
    Type: Grant
    Filed: September 28, 2023
    Date of Patent: February 11, 2025
    Assignee: Kingston Digital, Inc.
    Inventor: Hui-Hsin Lu
  • Patent number: D1065197
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: March 4, 2025
    Assignee: Kingston Digital, Inc.
    Inventor: Hui-Hsin Lu
  • Patent number: D1066274
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: March 11, 2025
    Assignee: Kingston Digital, Inc.
    Inventor: Hui-Hsin Lu
  • Patent number: D1070863
    Type: Grant
    Filed: December 20, 2022
    Date of Patent: April 15, 2025
    Assignee: KINGSTON DIGITAL, INC.
    Inventor: Hui-Hsin Lu