Patents by Inventor Hsiu-Jen Lin

Hsiu-Jen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10276548
    Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Shien Chen, Hsiu-Jen Lin, Ming-Chih Yew, Ming-Da Cheng, Yi-Jen Lai, Yu-Tse Su, Sey-Ping Sun, Yang-Che Chen
  • Patent number: 10276536
    Abstract: Structures and formation methods of a chip package are provided. The method includes forming a protective layer to surround a semiconductor die, and the protective layer has opposing first and second surfaces. The method also includes forming a dielectric layer over the first surface of the protective layer and the semiconductor die. The method further includes forming a conductive feature over the dielectric layer such that the conductive feature is electrically connected to a conductive element of the semiconductor die. In addition, the method includes printing a warpage-control element over the second surface of the protective layer and the semiconductor die such that the semiconductor die is between the warpage-control element and the dielectric layer.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hao-Jan Pei, Chih-Chiang Tsao, Wei-Yu Chen, Hsiu-Jen Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
  • Patent number: 10269739
    Abstract: Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Lun Chang, Chung-Shi Liu, Hsiu-Jen Lin, Hsien-Wei Chen, Ming-Da Cheng, Wei-Yu Chen
  • Publication number: 20190115326
    Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 18, 2019
    Inventors: Chen-Shien Chen, Hsiu-Jen Lin, Ming-Chih Yew, Ming-Da Cheng, Yi-Jen Lai, Yu-Tse Su, Sey-Ping Sun, Yang-Che Chen
  • Publication number: 20190096839
    Abstract: According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.
    Type: Application
    Filed: November 26, 2018
    Publication date: March 28, 2019
    Inventors: Wei-Hung Lin, Hsiu-Jen Lin, Ming-Da Cheng, Yu-Min Liang, Chen-Shien Chen, Chung-Shi Liu
  • Patent number: 10157862
    Abstract: An integrated fan-out package including an integrated circuit component, an insulating encapsulation, a redistribution circuit structure and a plurality of conductive terminals is provided. The insulating encapsulation laterally encapsulates sidewalls of the integrated circuit component. The redistribution circuit structure is disposed on the insulating encapsulation and the integrated circuit component. The redistribution circuit structure is electrically connected to the integrated circuit component and the redistribution circuit structure includes a plurality of ball pads. Each of the conductive terminals includes a conductive ball and a ring-shaped flux structure, wherein each of the conductive balls is disposed on and electrically connected to one of the ball pads. Each of the ring-shaped flux structures is disposed on the redistribution circuit structure. Each of the ring-shaped flux structure is disposed around and in contact with a bottom portion of the conductive ball.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Yu Chen, Ching-Hua Hsieh, Chung-Shi Liu, Hsiu-Jen Lin, Chia-Lun Chang
  • Publication number: 20180358325
    Abstract: Tools and systems for processing semiconductor devices, and methods of processing semiconductor devices are disclosed. In some embodiments, a method of using a tool for processing semiconductor devices includes a tool with a second material disposed over a first material, and a plurality of apertures disposed within the first material and the second material. The second material comprises a higher reflectivity than the first material. Each of the apertures is adapted to retain a package component over a support during an exposure to energy.
    Type: Application
    Filed: July 31, 2018
    Publication date: December 13, 2018
    Inventors: Kuei-Wei Huang, Hsiu-Jen Lin, Ai-Tee Ang, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 10153180
    Abstract: A system and method for applying an underfill is provided. An embodiment comprises applying an underfill to a substrate and patterning the underfill. Once patterned other semiconductor devices, such as semiconductor dies or semiconductor packages may then be attached to the substrate through the underfill, with electrical connections from the other semiconductor devices extending into the pattern of the underfill.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: December 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Hsiu-Jen Lin, Wei-Hung Lin, Kuei-Wei Huang, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 10141281
    Abstract: According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Hung Lin, Hsiu-Jen Lin, Ming-Da Cheng, Yu-Min Liang, Chen-Shien Chen, Chung-Shi Liu
  • Patent number: 10134703
    Abstract: A method of packaging includes placing a package component over a release film, wherein solder regions on a surface of the package component are in physical contact with the release film. Next, A molding compound filled between the release film and the package component is cured, wherein during the step of curing, the solder regions remain in physical contact with the release film.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Wei-Hung Lin, Sheng-Yu Wu, Bor-Ping Jang, Ming-Da Cheng, Chung-Shi Liu, Hsiu-Jen Lin, Wen-Hsiung Lu, Chih-Wei Lin, Yu-Peng Tsai, Kuei-Wei Huang, Chun-Cheng Lin
  • Publication number: 20180330970
    Abstract: A system and method for applying an underfill is provided. An embodiment comprises applying an underfill to a substrate and patterning the underfill. Once patterned other semiconductor devices, such as semiconductor dies or semiconductor packages may then be attached to the substrate through the underfill, with electrical connections from the other semiconductor devices extending into the pattern of the underfill.
    Type: Application
    Filed: July 26, 2018
    Publication date: November 15, 2018
    Inventors: Meng-Tse Chen, Hsiu-Jen Lin, Wei-Hung Lin, Kuei-Wei Huang, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20180315728
    Abstract: Structures and formation methods of a chip package are provided. The method includes forming a protective layer to surround a semiconductor die, and the protective layer has opposing first and second surfaces. The method also includes forming a dielectric layer over the first surface of the protective layer and the semiconductor die. The method further includes forming a conductive feature over the dielectric layer such that the conductive feature is electrically connected to a conductive element of the semiconductor die. In addition, the method includes printing a warpage-control element over the second surface of the protective layer and the semiconductor die such that the semiconductor die is between the warpage-control element and the dielectric layer.
    Type: Application
    Filed: April 28, 2017
    Publication date: November 1, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hao-Jan PEI, Chih-Chiang TSAO, Wei-Yu CHEN, Hsiu-Jen LIN, Ming-Da CHENG, Ching-Hua HSIEH, Chung-Shi LIU
  • Patent number: 10109612
    Abstract: Tools and systems for processing semiconductor devices, and methods of processing semiconductor devices are disclosed. In some embodiments, a method of using a tool for processing semiconductor devices includes a tool with a second material disposed over a first material, and a plurality of apertures disposed within the first material and the second material. The second material comprises a higher reflectivity than the first material. Each of the apertures is adapted to retain a package component over a support during an exposure to energy.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: October 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Kuei-Wei Huang, Hsiu-Jen Lin, Ai-Tee Ang, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20180286823
    Abstract: A method of forming a package structure includes disposing a semiconductor device over a first dielectric layer, wherein a first redistribution line is in the first dielectric layer, forming a molding compound over the first dielectric layer and in contact with a sidewall of the semiconductor device, forming a second dielectric layer over the molding compound and the semiconductor device, forming a first opening in the second dielectric layer, the molding compound, and the first dielectric layer to expose the first redistribution line, and forming a first conductor in the first opening, wherein the first conductor is electrically connected to the first redistribution line.
    Type: Application
    Filed: October 5, 2017
    Publication date: October 4, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hsuan TAI, Ting-Ting KUO, Yu-Chih HUANG, Chih-Wei LIN, Hsiu-Jen LIN, Chih-Hua CHEN, Ming-Da CHENG, Ching-Hua HSIEH, Hao-Yi TSAI, Chung-Shi LIU
  • Patent number: 10074615
    Abstract: A package structure including at least one conductive plate, a redistribution layer, a first semiconductor chip, a conductive shielding structure and an insulating encapsulant is provided. The first semiconductor chip is sandwiched in between the at least one conductive plate and the redistribution layer, wherein the first semiconductor chip is disposed on the at least one conductive plate and electrically connected to the redistribution layer. The conductive shielding structure is sandwiched in between the at least one conductive plate and the redistribution layer, wherein the conductive shielding structure surrounds the first semiconductor chip and electrically connects the at least one conductive plate with the redistribution layer. The insulating encapsulant is disposed on the redistribution layer, encapsulating the first semiconductor chip, the conductive shielding structure, and surrounding the at least one conductive plate.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: September 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Cheng Tseng, Chih-Hua Chen, Hsiu-Jen Lin, Hao-Yi Tsai, Kuo-Chung Yee, Chia-Hung Liu
  • Publication number: 20180211928
    Abstract: Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.
    Type: Application
    Filed: March 27, 2018
    Publication date: July 26, 2018
    Inventors: Chia-Lun Chang, Chung-Shi Liu, Hsiu-Jen Lin, Hsien-Wei Chen, Ming-Da Cheng, Wei-Yu Chen
  • Publication number: 20180197847
    Abstract: A package includes a package component, which further includes a top surface and a metal pad at the top surface of the package component. The package further includes a non-reflowable electrical connector over and bonded to the metal pad, and a molding material over the package component. The non-reflowable electrical connector is molded in the molding material and in contact with the molding material. The non-reflowable electrical connector has a top surface lower than a top surface of the molding compound.
    Type: Application
    Filed: March 6, 2018
    Publication date: July 12, 2018
    Inventors: Kuei-Wei Huang, Chih-Wei Lin, Hsiu-Jen Lin, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20180166421
    Abstract: A structure includes a first package and a second package. The second package is coupled to the first package by one or more connectors. Epoxy flux residue is disposed around the connectors and in contact with the connectors. A method includes providing a first package having first connector pads and providing a second package having corresponding second connector pads. Solder paste is printed on each of the first connector pads. Epoxy flux is printed on each of the solder paste. The first and second connector pads are aligned and the packages are pressed together. The solder paste is reflowed to connect the first connector pads to the second connector pads while leaving an epoxy flux residue around each of the connections.
    Type: Application
    Filed: January 29, 2018
    Publication date: June 14, 2018
    Inventors: Chen-Hua Yu, Wei-Yu Chen, Kuei-Wei Huang, Hsiu-Jen Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu, Hsuan-Ting Kuo
  • Publication number: 20180166308
    Abstract: Presented herein is a device processing boat comprising a base and at least one unit retainer disposed in the base. The device further comprises a cover having at least one recess configured to accept and retain at least one unit. The at least one recess is aligned over, and configured to hold the at least one unit over, at least a portion of the at least one unit retainer. The cover is retained to the device processing boat by the at least one unit retainer. At least one pressure sensor having at least one sensel is disposed in the base. The sensel is configured to sense a clamping force applied by the cover to the at least one unit.
    Type: Application
    Filed: February 9, 2018
    Publication date: June 14, 2018
    Inventors: Ai-Tee Ang, Hsiu-Jen Lin, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20180151523
    Abstract: A conductive interconnect structure includes a contact pad; a conductive body connected to the contact pad at a first end; and a conductive layer positioned on a second end of the conductive body. The conductive body has a longitudinal direction perpendicular to a surface of the contact pad. The conductive body has an average grain size (a) on a cross sectional plane (Plane A) whose normal is perpendicular to the longitudinal direction of the conductive body. The conductive layer has an average grain size (b) on Plane A. The conductive body and the conductive layer are composed of same material, and the average grain size (a) is greater than the average grain size (b).
    Type: Application
    Filed: January 23, 2018
    Publication date: May 31, 2018
    Inventors: MENG-TSE CHEN, HSIU-JEN LIN, CHIH-WEI LIN, MING-DA CHENG, CHIH-HANG TUNG, CHUNG-SHI LIU