Patents by Inventor Hsiu-Jen Lin

Hsiu-Jen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Package structure and method for manufacturing the same
    Patent number: 9978716
    Abstract: A package structure includes a molding material, at least one through-via, at least one conductor, at least one dummy structure and an underfill. The through-via extends through the molding material. The conductor is present on the through-via. The dummy structure is present on the molding material and includes a dielectric material. The underfill is at least partially present between the conductor and the dummy structure.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: May 22, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chiang Tsao, Hsiu-Jen Lin, Chun-Cheng Lin, Chih-Wei Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
  • Package-on-package structures and methods for forming the same
    Patent number: 9935091
    Abstract: A package includes a package component, which further includes a top surface and a metal pad at the top surface of the package component. The package further includes a non-reflowable electrical connector over and bonded to the metal pad, and a molding material over the package component. The non-reflowable electrical connector is molded in the molding material and in contact with the molding material. The non-reflowable electrical connector has a top surface lower than a top surface of the molding compound.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Wei Huang, Chih-Wei Lin, Hsiu-Jen Lin, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Semiconductor packaging and manufacturing method thereof
    Patent number: 9935044
    Abstract: The present disclosure provides a semiconductor package includes a contact pad, a device external to the contact pad and a solder bump on the contact pad. The device has a conductive contact pad corresponding to the contact pad. The solder bump connects the contact pad with the conductive contact pad. The solder bump comprises a height from a top of the solder bump to the contact pad; and a width which is a widest dimension of the solder bump in a direction perpendicular to the height. A junction portion of the solder bump in proximity to the contact pad comprises an hourglass shape.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: April 3, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiu-Jen Lin, Wen-Hsiung Lu, Cheng-Ting Chen, Hsuan-Ting Kuo, Wei-Yu Chen, Ming-Da Cheng, Chung-Shi Liu
  • Methods of forming connector pad structures, interconnect structures, and structures thereof
    Patent number: 9935067
    Abstract: Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company LTD.
    Inventors: Chia-Lun Chang, Chung-Shi Liu, Hsiu-Jen Lin, Hsien-Wei Chen, Ming-Da Cheng, Wei-Yu Chen
  • Dicing in wafer level package
    Patent number: 9929071
    Abstract: A package includes a device die, and an encapsulating material encircling the device die. The encapsulating material includes a first portion with a substantially uniform first width, and a second portion lower than the first portion. Lower portions of the second portion have second widths increasingly smaller than widths of respective overlying upper portions of the second portion. The package further includes at least one dielectric layer underlying and in contact with the encapsulating material. The at least one dielectric layer has third widths smaller than the substantially uniform first width. The substantially uniform first width, the second widths, and the third widths are measured in a cross-sectional view of the package, and are measured in directions parallel to a major top surface of the encapsulating material.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: March 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Shen Cheng, An-Jhih Su, Chung-Shi Liu, Hsiu-Jen Lin, Hsien-Wei Chen, Ming-Da Cheng, Wei-Yu Chen
  • Semiconductor Packages having Dummy Connectors and Methods of Forming Same
    Publication number: 20180076184
    Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.
    Type: Application
    Filed: August 4, 2017
    Publication date: March 15, 2018
    Inventors: Chen-Shien Chen, Hsiu-Jen Lin, Ming-Chih Yew, Ming-Da Cheng, Yi-Jen Lai, Yu-Tse Su, Sey-Ping Sun, Yang-Che Chen
  • Semiconductor processing boat design with pressure sensor
    Patent number: 9911633
    Abstract: Presented herein is a device processing boat comprising a base and at least one unit retainer disposed in the base. The device further comprises a cover having at least one recess configured to accept and retain at least one unit. The at least one recess is aligned over, and configured to hold the at least one unit over, at least a portion of the at least one unit retainer. The cover is retained to the device processing boat by the at least one unit retainer. At least one pressure sensor having at least one sensel is disposed in the base. The sensel is configured to sense a clamping force applied by the cover to the at least one unit.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: March 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ai-Tee Ang, Hsiu-Jen Lin, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Systems for processing semiconductor devices, and methods of processing semiconductor devices
    Patent number: 9888527
    Abstract: Systems for processing semiconductor devices, and methods of processing semiconductor devices are disclosed. In some embodiments, a system for processing semiconductor devices includes a radiation energy source, a support, and a tool disposable between the support and the radiation energy source. The tool includes apertures adapted to retain a package component over the support. The system includes a cooling device proximate the support.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: February 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiu-Jen Lin, Wei-Yu Chen, Ai-Tee Ang, Ming-Da Cheng, Chung-Shi Liu
  • Package-on-package structure with epoxy flux residue
    Patent number: 9881903
    Abstract: A structure includes a first package and a second package. The second package is coupled to the first package by one or more connectors. Epoxy flux residue is disposed around the connectors and in contact with the connectors. A method includes providing a first package having first connector pads and providing a second package having corresponding second connector pads. Solder paste is printed on each of the first connector pads. Epoxy flux is printed on each of the solder paste. The first and second connector pads are aligned and the packages are pressed together. The solder paste is reflowed to connect the first connector pads to the second connector pads while leaving an epoxy flux residue around each of the connections.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: January 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wei-Yu Chen, Kuei-Wei Huang, Hsiu-Jen Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu, Hsuan-Ting Kuo
  • Manufacturing method of interconnect structure
    Patent number: 9881888
    Abstract: A conductive interconnect structure includes a contact pad; a conductive body connected to the contact pad at a first end; and a conductive layer positioned on a second end of the conductive body. The conductive body has a longitudinal direction perpendicular to a surface of the contact pad. The conductive body has an average grain size (a) on a cross sectional plane (Plane A) whose normal is perpendicular to the longitudinal direction of the conductive body. The conductive layer has an average grain size (b) on Plane A. The conductive body and the conductive layer are composed of same material, and the average grain size (a) is greater than the average grain size (b).
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: January 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Meng-Tse Chen, Hsiu-Jen Lin, Chih-Wei Lin, Ming-Da Cheng, Chih-Hang Tung, Chung-Shi Liu
  • STUD BUMP STRUCTURE FOR SEMICONDUCTOR PACKAGE ASSEMBLIES
    Publication number: 20180005973
    Abstract: A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure.
    Type: Application
    Filed: September 18, 2017
    Publication date: January 4, 2018
    Inventors: Meng-Tse CHEN, Hsiu-Jen LIN, Chih-Wei LIN, Cheng-Ting CHEN, Ming-Da CHENG, Chung-Shi LIU
  • PACKAGE-ON-PACKAGE STRUCTURE WITH EPOXY FLUX RESIDUE
    Publication number: 20170345794
    Abstract: A structure includes a first package and a second package. The second package is coupled to the first package by one or more connectors. Epoxy flux residue is disposed around the connectors and in contact with the connectors. A method includes providing a first package having first connector pads and providing a second package having corresponding second connector pads. Solder paste is printed on each of the first connector pads. Epoxy flux is printed on each of the solder paste. The first and second connector pads are aligned and the packages are pressed together. The solder paste is reflowed to connect the first connector pads to the second connector pads while leaving an epoxy flux residue around each of the connections.
    Type: Application
    Filed: August 4, 2016
    Publication date: November 30, 2017
    Inventors: Chen-Hua Yu, Wei-Yu Chen, Kuei-Wei Huang, Hsiu-Jen Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu, Hsuan-Ting Kuo
  • PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20170317054
    Abstract: A package structure includes a molding material, at least one through-via, at least one conductor, at least one dummy structure and an underfill. The through-via extends through the molding material. The conductor is present on the through-via. The dummy structure is present on the molding material and includes a dielectric material. The underfill is at least partially present between the conductor and the dummy structure.
    Type: Application
    Filed: August 15, 2016
    Publication date: November 2, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chiang TSAO, Hsiu-Jen LIN, Chun-Cheng LIN, Chih-Wei LIN, Ming-Da CHENG, Ching-Hua HSIEH, Chung-Shi LIU
  • Stud bump structure for semiconductor package assemblies
    Patent number: 9768137
    Abstract: A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Hsiu-Jen Lin, Chih-Wei Lin, Cheng-Ting Chen, Ming-Da Cheng, Chung-Shi Liu
  • Methods of Forming Connector Pad Structures, Interconnect Structures, and Structures Thereof
    Publication number: 20170154862
    Abstract: Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.
    Type: Application
    Filed: February 13, 2017
    Publication date: June 1, 2017
    Inventors: Chia-Lun Chang, Chung-Shi Liu, Hsiu-Jen Lin, Hsien-Wei Chen, Ming-Da Cheng, Wei-Yu Chen
  • Packages and methods for forming the same
    Patent number: 9627369
    Abstract: A device includes a package component having conductive features on a top surface, and a polymer region molded over the top surface of the first package component. A plurality of openings extends from a top surface of the polymer region into the polymer region, wherein each of the conductive features is exposed through one of the plurality of openings. The plurality of openings includes a first opening having a first horizontal size, and a second opening having a second horizontal size different from the first horizontal size.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Chun-Cheng Lin, Yu-Peng Tsai, Hsiu-Jen Lin, Ming-Da Cheng, Chung-Shi Liu
  • Warpage Control in the Packaging of Integrated Circuits
    Publication number: 20170098571
    Abstract: A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.
    Type: Application
    Filed: December 15, 2016
    Publication date: April 6, 2017
    Inventors: Ming-Da Cheng, Hsiu-Jen Lin, Cheng-Ting Chen, Wei-Yu Chen, Chien-Wei Lee, Chung-Shi Liu
  • Package on package interconnect structure
    Patent number: 9607921
    Abstract: A structure comprises a post passivation interconnect layer formed over a semiconductor substrate, a metal bump formed over the post passivation interconnect layer and a molding compound layer formed over the semiconductor substrate. A lower portion of the metal bump is embedded in the molding compound layer and a middle portion of the metal bump is surrounded by a concave meniscus molding compound protection layer.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: March 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hsiung Lu, Yi-Wen Wu, Chih-Wei Lin, Hsiu-Jen Lin, Ming-Da Cheng, Chung-Shi Liu
  • Dicing in Wafer Level Package
    Publication number: 20170062300
    Abstract: A package includes a device die, and an encapsulating material encircling the device die. The encapsulating material includes a first portion with a substantially uniform first width, and a second portion lower than the first portion. Lower portions of the second portion have second widths increasingly smaller than widths of respective overlying upper portions of the second portion. The package further includes at least one dielectric layer underlying and in contact with the encapsulating material. The at least one dielectric layer has third widths smaller than the substantially uniform first width. The substantially uniform first width, the second widths, and the third widths are measured in a cross-sectional view of the package, and are measured in directions parallel to a major top surface of the encapsulating material.
    Type: Application
    Filed: October 31, 2016
    Publication date: March 2, 2017
    Inventors: Chia-Shen Cheng, An-Jhih Su, Chung-Shi Liu, Hsiu-Jen Lin, Hsien-Wei Chen, Ming-Da Cheng, Wei-Yu Chen
  • Methods of forming connector pad structures, interconnect structures, and structures thereof
    Patent number: 9570410
    Abstract: Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: February 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Lun Chang, Chung-Shi Liu, Hsiu-Jen Lin, Hsien-Wei Chen, Ming-Da Cheng, Wei-Yu Chen