Patents by Inventor Hsiung Hsu

Hsiung Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220309810
    Abstract: A method and apparatus for morphological analysis of neural cells may include receiving an immunohistochemistry (IHC) image of one or more neural cells; detecting the one or more neural cells in the IHC image using a first neural network, wherein the detecting includes identifying boundaries of the one or more neural cells; generating a segmentation cell mask using a second neural network based on the identified boundaries of the one or more neural cells; and classifying the one or more neural cells based on the generated segmentation cell mask using a trained classification model.
    Type: Application
    Filed: March 28, 2022
    Publication date: September 29, 2022
    Applicant: HOWARD UNIVERSITY
    Inventors: Tsang-Wei TU, Yi-YU HSU, Chao-Hsiung HSU, Artur AGARONYAN, Paul C. WANG
  • Patent number: 11429028
    Abstract: A method includes: providing a first layout of a first layer over a substrate, the first layer having at least one metal pattern, and generating a second layout by placing a cut mask at a first position relative to the substrate to remove material from a first region of the at least one metal pattern to provide a first metal pattern and placing the cut mask at a second position relative to the first layer over the substrate to remove material from a second region of the at least one metal pattern to provide a second metal pattern.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: August 30, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Hsiung Hsu, Huang-Yu Chen, Tsong-Hua Ou, Wen-Hao Chen
  • Publication number: 20220211999
    Abstract: An artificial retinal prosthesis is disclosed, which comprises a plurality of pixel group units to output a spatiotemporal electrical stimulation for inducing color perception. Each of the pixel group units comprises a main pixel unit and at least one surrounding pixel unit. The main pixel unit and the surrounding pixel unit respectively outputs an electrical stimulation waveform according to a first stimulation cycle and a second stimulation cycle. Both of the first stimulation cycle and the second stimulation cycle have a first-half duration and a second-half duration. The first-half duration of the first stimulation cycle has inactive period greater than 20% and less than 80% and the rest of the first stimulation cycle is active period. The second-half duration of the first stimulation cycle is inactive period. The first-half duration of the second stimulation cycle is active period and the second-half duration of the second stimulation cycle is inactive period.
    Type: Application
    Filed: March 25, 2022
    Publication date: July 7, 2022
    Inventors: Feng-Hsiung HSU, Yung-Chan CHEN, Long-Sheng FAN, Lee LIN
  • Publication number: 20220212011
    Abstract: An artificial prosthesis is disclosed, which comprises a pixel array, a correlated double sampling unit, an analog-to-digital converter, a digital core, and a digital-to-analog converter. The digital core is configured to perform a calculation of electrical stimulation waveform of each of the pixels by using a processing function of an ANN. As such, the neural stimulation levels for artificial vision can be optimized.
    Type: Application
    Filed: March 25, 2022
    Publication date: July 7, 2022
    Inventors: Feng-Hsiung HSU, Yung-Chan CHEN, Long-Sheng FAN
  • Patent number: 11349262
    Abstract: An electrical connector assembly comprising: an insulative housing with a front mating slot and a rear receiving cavity; a combo contact module assembly received within the receiving cavity and including a sideband contact module sandwiched between a pair of high speed contact modules; each high speed contact module including an upper unit and a lower unit assembled with each other in a vertical direction; the upper unit and the lower unit being essentially symmetrically arranged with each other in the vertical direction with a half of pitch offset in a transverse direction; and a metallic shell; wherein each of the upper unit and the lower unit including a front subunit and a rear subunit stacked with each other in the vertical direction and retained together.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: May 31, 2022
    Assignees: FOXCONN (KUNSHAN) COMPUTER CONNECTOR CO., LTD., FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventors: Chih-Ping Chung, Chun-Hsiung Hsu, Kuei-Chung Tsai, Terrance F. Little
  • Publication number: 20220158388
    Abstract: An electrical connector includes: an insulating body; and a first row of terminals and a second row of terminals housed in the insulating body, each terminal in the first row of terminals having a tail portion, a contact portion, and a body portion, the first row of terminals including a signal terminal pair having a pair of signal terminals and a ground terminal arranged on one side of the signal terminal pair, wherein a first center distance between the contact portions of the signal terminal pair is different from a second center distance between the contact portion of the ground terminal and the contact portion of an adjacent signal terminal.
    Type: Application
    Filed: November 12, 2021
    Publication date: May 19, 2022
    Inventors: CHIH-PING CHUNG, CHUN-HSIUNG HSU, KUEI-CHUNG TSAI
  • Patent number: 11251801
    Abstract: A frequency adjusting apparatus used in a processing chip operated at an operation frequency according to a power is provided that includes a clock supplying circuit, a frequency division circuit and a control circuit. The clock supplying circuit outputs one of clock signals as a supplied clock signal. The frequency division circuit performs frequency division on the supplied clock signal according to a parameter to generate an output clock signal. The control circuit determines a combination of a selected clock signal and a value of the parameter for gradually increasing the frequency of the output clock signal during the increasing of the voltage value that passes through voltage value sections, wherein when the voltage value is determined to be larger than a second threshold value and when the voltage value sections correspond to higher voltage values, the selected clock signal has a higher frequency.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: February 15, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chih-Hsiung Hsu, Gerchih Chou, Han-Chieh Hsieh
  • Publication number: 20220045459
    Abstract: An electrical connector assembly includes a board connector and a cable connector. The board connector includes a first seat comprising a base and two first sidewalls commonly defining a mating space, and a pair of first locking portions with locking heads projecting into the mating space, and a plurality of first terminals retained in the first seat and comprising contacting portions projecting into the mating space and leg portions. The cable connector includes a second seat including a pair of second locking portions to engage with the first locking portions and plural second terminals retained in the second seat. The first seat of the board connector further includes a second sidewall unitarily connecting with the base and first sidewalls at a same side and the second sidewall defines a first locking section to engage with a second locking section defined on the cable connector.
    Type: Application
    Filed: August 5, 2021
    Publication date: February 10, 2022
    Inventors: XIAO-JUAN LIN, CHUN-HSIUNG HSU
  • Publication number: 20210351536
    Abstract: An electrical connector assembly comprising: an insulative housing with a front mating slot and a rear receiving cavity; a combo contact module assembly received within the receiving cavity and including a sideband contact module sandwiched between a pair of high speed contact modules; each high speed contact module including an upper unit and a lower unit assembled with each other in a vertical direction; the upper unit and the lower unit being essentially symmetrically arranged with each other in the vertical direction with a half of pitch offset in a transverse direction; and a metallic shell; wherein each of the upper unit and the lower unit including a front subunit and a rear subunit stacked with each other in the vertical direction and retained together.
    Type: Application
    Filed: August 5, 2020
    Publication date: November 11, 2021
    Inventors: CHIH-PING CHUNG, CHUN-HSIUNG HSU, KUEI-CHUNG TSAI, TERRANCE F. LITTLE
  • Publication number: 20210320448
    Abstract: An electrical connector includes an insulating body, a first terminal group having a signal terminal pair and a ground terminal arranged on one side of the signal terminal pair, each signal terminal having a tail portion, a contact portion, and a body portion, the body portion having a covering portion and a free portion exposed to air, wherein there is a first center distance between the contact portions of the signal terminal pair, there is a second center distance between the free portions, and there is a third center distance between the covering parts, and a second terminal group forming a first mating port with the first terminal group, wherein the second center distance is smaller than the first center distance, and the third center distance is greater than the second center distance.
    Type: Application
    Filed: April 6, 2021
    Publication date: October 14, 2021
    Inventors: CHIH-PING CHUNG, KUEI-CHUNG TSAI, CHUN-HSIUNG HSU
  • Publication number: 20210143826
    Abstract: A frequency adjusting apparatus used in a processing chip operated at an operation frequency according to a power is provided that includes a clock supplying circuit, a frequency division circuit and a control circuit. The clock supplying circuit outputs one of clock signals as a supplied clock signal. The frequency division circuit performs frequency division on the supplied clock signal according to a parameter to generate an output clock signal. The control circuit determines a combination of a selected clock signal and a value of the parameter for gradually increasing the frequency of the output clock signal during the increasing of the voltage value that passes through voltage value sections, wherein when the voltage value is determined to be larger than a second threshold value and when the voltage value sections correspond to higher voltage values, the selected clock signal has a higher frequency.
    Type: Application
    Filed: November 11, 2019
    Publication date: May 13, 2021
    Inventors: Chih-Hsiung Hsu, Gerchih Chou, Han-Chieh Hsieh
  • Patent number: 10916891
    Abstract: An electrical connector (100) includes an insulative housing (1), a plurality of contacts received in the insulative housing, and a first conductive member (24). The contacts include a pair of first grounding contacts (212) for transmitting grounding signal, and a pair of first signal contacts (211) for transmitting a differential signal. The pair of first grounding contacts and the pair of first signal contacts are arranged in a first row. The pair of first signal contacts is disposed between the pair of first grounding contacts. The first conductive member is electrically connected with both of the first grounding contacts in at least two different locations.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: February 9, 2021
    Assignees: FOXCONN (KUNSHAN) COMPUTER CONNECTOR CO., LTD., FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventors: Chun-Hsiung Hsu, Kuei-Chung Tsai
  • Patent number: 10891410
    Abstract: In an example embodiment, a computer-implemented method is provided for receiving an integrated circuit design, wherein the integrated circuit design comprises at least one position in violation of one or more design rules associated with the integrated design, identifying one or more design patterns at the at least one violating position, generating one or more pattern graphs for the one or more design patterns, extracting a system on chip design for transformation into a block graph, and. comparing the block graph with each of the one or more pattern graphs to determine whether the at least one violating position is cleared. In circumstances where a match is found between the block graph and the each of the one or more pattern graphs, the computer-implemented method further comprises changing the one or more design patterns and repeating the step of comparing until there is no further match found.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: January 12, 2021
    Assignee: Synopsys, Inc.
    Inventors: Chin-Hsiung Hsu, Philip Hui-Yuh Tai, Sheng-Wei Yang, Guo-Ting Wang
  • Publication number: 20200206212
    Abstract: Provided herein are formulations and methods of use of 2-(4-chlorophenyl)-N-((2-(2,6-dioxopiperidin-3-yl)-1-oxoisoindolin-5-yl)methyl)-2,2-difluoroacetamide or a stereoisomer or mixture of stereoisomers, pharmaceutically acceptable salt, tautomer, prodrug, isotopologue, solvate, hydrate, co-crystal, clathrate, or polymorph thereof.
    Type: Application
    Filed: December 30, 2019
    Publication date: July 2, 2020
    Inventors: Rowena Fernandez Choudrie, Willard Foss, Che-Hsiung Hsu, Amol Mungikar, Yu Pu
  • Publication number: 20200203892
    Abstract: An electrical connector (100) includes an insulative housing (1), a plurality of contacts received in the insulative housing, and a first conductive member (24). The contacts include a pair of first grounding contacts (212) for transmitting grounding signal, and a pair of first signal contacts (211) for transmitting a differential signal. The pair of first grounding contacts and the pair of first signal contacts are arranged in a first row. The pair of first signal contacts is disposed between the pair of first grounding contacts. The first conductive member is electrically connected with both of the first grounding contacts in at least two different locations.
    Type: Application
    Filed: March 3, 2020
    Publication date: June 25, 2020
    Inventors: CHUN-HSIUNG HSU, KUEI-CHUNG TSAI
  • Publication number: 20200081348
    Abstract: A method includes: providing a first layout of a first layer over a substrate, the first layer having at least one metal pattern, and generating a second layout by placing a cut mask at a first position relative to the substrate to remove material from a first region of the at least one metal pattern to provide a first metal pattern and placing the cut mask at a second position relative to the first layer over the substrate to remove material from a second region of the at least one metal pattern to provide a second metal pattern.
    Type: Application
    Filed: November 13, 2019
    Publication date: March 12, 2020
    Inventors: Chin-Hsiung Hsu, Huang-Yu Chen, Tsong-Hua Ou, Wen-Hao Chen
  • Publication number: 20200069945
    Abstract: The present invention discloses a high density retinal prosthesis system with equalization comprises a retinal prosthesis chip, a measuring device, a tuning device, and a transmitting device. After the measuring device capable of generating electrical induction with the retinal prosthesis chip obtains a degree of light stimulation received by pixel units in the retinal prosthesis chip, it is equalized by the tuning device, and then a calibration signal is fed to the pixel units to tune the pixel units to make the pixel units in the retinal prosthesis system to achieve an equalization effect.
    Type: Application
    Filed: August 27, 2019
    Publication date: March 5, 2020
    Inventors: LONG-SHENG FAN, FENG-HSIUNG HSU, YUNG-CHAN CHEN
  • Patent number: 10581201
    Abstract: An electrical connector (100) includes an insulative housing (1), a plurality of contacts received in the insulative housing, and a first conductive member (24). The contacts include a pair of first grounding contacts (212) for transmitting grounding signal, and a pair of first signal contacts (211) for transmitting a differential signal. The pair of first grounding contacts and the pair of first signal contacts are arranged in a first row. The pair of first signal contacts is disposed between the pair of first grounding contacts. The first conductive member is electrically connected with both of the first grounding contacts in at least two different locations.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: March 3, 2020
    Assignees: FOXCONN (KUNSHAN) COMPUTER CONNECTOR CO., LTD., FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventors: Chun-Hsiung Hsu, Kuei-Chung Tsai
  • Patent number: 10575441
    Abstract: An electrical connector assembly includes: a metal shell including a top wall, a bottom wall, a pair of parallel spaced side walls connecting the top and bottom walls, a receiving space, and a front opening communicating with the receiving space; a connector received in the receiving space of the metal shell; and a heat sink disposed in the rear side of the metal shell, wherein the metal shell includes a rear opening communicating with the receiving space, and the heat sink covers the rear opening.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: February 25, 2020
    Assignees: FOXCONN (KUNSHAN) COMPUTER CONNECTOR CO., LTD, FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventor: Chun-Hsiung Hsu
  • Patent number: 10509322
    Abstract: A method includes patterning a layer over a substrate with a first metal pattern; using a cut mask in a first position relative to the substrate to perform a first cut patterning for removing material from a first region within the first pattern; and using the same cut mask to perform a second cut patterning while in a second position relative to the same layer over the substrate, for removing material from a second region in a second metal pattern of the same layer over the substrate.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Hsiung Hsu, Huang-Yu Chen, Tsong-Hua Ou, Wen-Hao Chen