Abstract: Technologies pertaining to computing depth images of a scene that includes a mobile object based upon the principle of light falloff are described herein. An infrared image of a scene that includes a mobile object is captured, wherein the infrared image has a plurality of pixels having a respective plurality of intensity values. A depth image for the scene is computed based at least in part upon square roots of respective intensity values in the infrared image.

Abstract: Computing devices are often designed in view of a particular usage scenario, but may be unsuitable for usage in other computing scenarios. For example, a notebook computer with a large display, an integrated keyboard, and a high-performance processor suitable for many computing tasks may be heavy, large, and power-inefficient; and a tablet lacking a keyboard and incorporating a low-powered processor may improve portability but may present inadequate performance for many tasks. Presented herein is a configuration of a computing device featuring a display unit with a resource-conserving processor that may be used independently (e.g., as a tablet), but that may be connected to a base unit featuring a resource-intensive processor. The operating system of the device may accordingly transition between a resource-intensive computing environment and a resource-conserving computing environment based on the connection with the base unit, thereby satisfying the dual roles of workstation and portable tablet device.

Abstract: A method for providing a macro placement of an integrated circuit is provided. An initial placement of the integrated circuit is obtained, wherein the initial placement includes a plurality of first macro blocks. The first macro blocks are divided into a plurality of groups according to the hierarchy of the integrated circuit. A value of layout area is obtained for each of the groups according to macro areas of the first macro blocks. A plurality of candidate placements are obtained for each of the groups according to the value of placement area corresponding to the group, wherein the candidate placement includes the first macro blocks corresponding to the group. A first macro placement is obtained according to a specific placement o selecting from the candidate placements for each of the groups.

Abstract: A method includes patterning a layer over a substrate with a first metal pattern; using a cut mask in a first position relative to the substrate to perform a first cut patterning for removing material from a first region within the first pattern; and using the same cut mask to perform a second cut patterning while in a second position relative to the same layer over the substrate, for removing material from a second region in a second metal pattern of the same layer over the substrate.

Abstract: A method for redistributing cell densities in layout of IC is provided. Initial cell density distribution and routing density distribution are obtained in an initial placement of the IC. White space is inserted into the initial placement according to a specific density value, so as to flatten the initial cell density distribution to the specific density value and obtain a flat cell density distribution. The specific density value is larger than a maximum cell density value within the initial cell density distribution. Cell densities of a first region are increased in the IC according to the routing density distribution and the flat cell density distribution, so as to obtain a modified cell density distribution. The modified cell density distribution is smoothed to obtain a calibrated cell density distribution. The white space is removed from the calibrated cell density distribution to obtain a final placement.

Abstract: A method for reducing congestion regions of an integrated circuit is provided. A placement of the IC is obtained, wherein the placement includes a signal path between a first macro module and a second macro module. The signal path passes through a routing area of the placement for transmitting a specific signal. A congestion region of the routing area is identified. The signal path includes at least one cell or routing path in the congestion region. A cost evaluation is obtained for each candidate position of the routing area by moving the cell or the routing path out of the congestion region. The cell is moved to the candidate position having a minimum cost evaluation among the cost evaluations. The placement and the routing paths are simultaneously updated according to the cell moved to the candidate position having the minimum cost evaluation.

Abstract: A method for creating double patterning compliant integrated circuit layouts is disclosed. The method allows patterns to be assigned to different masks and stitched together during lithography. The method also allows portions of the pattern to be removed after the process.

Abstract: A method includes patterning a layer over a substrate with a first metal pattern; using a cut mask in a first position relative to the substrate to perform a first cut patterning for removing material from a first region within the first pattern; and using the same cut mask to perform a second cut patterning while in a second position relative to the same layer over the substrate, for removing material from a second region in a second metal pattern of the same layer over the substrate.

Abstract: A method for minimizing layout area of IC is provided. A plurality of first tiles of an initial floor plan are obtained according to a plurality of partitions and channels of the initial floor plan. Each first tile between the partition and the channel has a fixed tile property being the partition or the channel. Each second tile between at least one of the partitions and at least one of the channels has a changeable tile property which can be changed between the at least one partition and the at least one channel. A specific area path of the layout area is obtained according to the partitions, the channels and the routing densities corresponding to the channels. The changeable tile properties of the second tiles are changed according to the specific area path, to re-shape the partitions and re-route the nets within the channels.

Abstract: Display components (e.g., liquid crystal displays (LCDs)) are viewable at different viewing angles, for example, by a first user positioned directly in front of the display and by a second user positioned to one side of the display. Many displays present a consistent display across a wide range of viewing angles, but these displays may consume energy and/or compromise user privacy. Presented herein are configurations of backlights for display devices featuring an adjustable viewing angle, such that a user may select a narrower viewing angle in usage scenarios involving power consumption or privacy, and may select a wider viewing angle in usage scenarios involving plentiful power and fewer privacy concerns. Such configurations may include multiple banks of backlight lamps generating backlight at different viewing angles; an electrowetting electrode as an adjustable collimator; adjustable diffusers that may adjustably scatter light passing therethrough; and/or a combination of such adjustable elements.

Abstract: A detachable hula hoop having waterproof reservoirs is provided with hollow arc sections each including a neck; a first connection end at a first end and including an opening, a channel, and a first recess on a surface; a plug including a cylindrical member and a head; a second connection end at a second end and including a closed member and a second recess on a surface; and a reservoir. The first recess is complimentarily disposed in the second recess to fasten the first and second connection ends together. The cylindrical member is disposed in the neck, the head urges against an annular shoulder to block the neck, and the head is urged against by the closed member.

Abstract: A compound circuit board for a radar device includes a first substrate including a plurality of trace layers having a first trace layer formed with a digital signal processing unit and an electronic control unit in a first area, a second substrate including a plurality of trace layers having a second trace layer formed with an antenna module in a second area, and a prepreg layer between the first and second substrates for connecting the first and second substrates, wherein the first area and the second area in a first projecting result generated by projecting the first trace layer on the second trace layer are substantially overlapped.

Abstract: A method identifies, as an independent node, any node representing a circuit pattern in any odd loop of a layout of a region of a layer of an IC that is not included in any other odd loop of the layout. The layer is to have a plurality of circuit patterns to be patterned using at least three photomasks. The method identifies, as a safe independent node, any independent node not closer than a threshold distance from any other independent nodes in another odd loop of the layout. The layout is modified, if the circuit patterns in the layout include any odd loop without any safe independent node, so that that after the modifying, each odd loop has at least one safe independent node.

Abstract: A radio-frequency transceiver system comprises a radio-frequency processing unit, a transmitting microwave network and a receiving microwave network, wherein the transmitting microwave network comprises a transmitting power divider for distributing main power of transmitting signals to two central sub-array antennas of four sub-array antennas, and the receiving microwave network comprises a receiving power divider for providing power mainly from a first input terminal and a second input terminal for a receiving route, and providing power mainly from the second input terminal and a third input terminal for another receiving route.

Abstract: Some embodiments of the present disclosure relates to a method and apparatus to achieve a layout that is compatible with a multiple-patterning process. Two or more unit cells are constructed with layouts which satisfy the properties of the multiple-patterning process, and are each decomposed into two or more colors to support the multiple-patterning process. An active layout feature is merged with a dummy wire at a shared boundary between two unit cells. In the event of a short between two active layout features at the shared boundary, an automatic post-layout method can rearrange the layout features in a vicinity of the shared boundary to separate the active layout features to achieve cell functionality while satisfying the multiple-patterning properties.

Abstract: A detachable hula hoop having waterproof reservoirs is provided with hollow arc sections each including a neck; a first connection end at a first end and including an opening, a channel, and a first recess on a surface; a plug including a cylindrical member and a head; a second connection end at a second end and including a closed member and a second recess on a surface; and a reservoir. The first recess is complimentarily disposed in the second recess to fasten the first and second connection ends together. The cylindrical member is disposed in the neck, the head urges against an annular shoulder to block the neck, and the head is urged against by the closed member.

Abstract: A portion of a layout of a single layer of an integrated circuit is to be multi-patterned. A method for layout decomposition includes determining spacings between adjacent pairs of patterns, and generating a conflict graph having a plurality of sub-graphs, in which a respective vertex corresponds to each respective sub-graph. The patterns within each respective sub-graph are divided into at least a first group and a second group, each of which is assigned to be patterned on the single layer by a respectively different one of a first mask or a second mask. The method further include determining, in a processor, a count of color-rule violations in the plurality of patterns within each respective sub-graph based on a predetermined set of criteria; and within each sub-graph, assigning the first group of patterns in the sub-graph to the one of the first mask or the second mask which results in a smaller count of color-rule violations.

Abstract: Disclosed are systems and methods associated with a touch-sensitive input device including a plurality of keys, wherein each key of the plurality of keys includes at least one spring. Such a spring may include a substantially planar peak located at a central portion of the spring, a first substantially arcuate leg extending from the peak in a first direction, and a second substantially arcuate leg extending from the peak in a second direction substantially perpendicular to the first direction. In one embodiment, a resistive force provided by the at least one spring decreases after the peak travels a first distance from an initial position of the peak. In such an embodiment, the first distance is less than or equal to approximately ? of a range of travel of the peak.

Abstract: Among other things, one or more techniques and/or systems for performing design layout are provided. In an example, a design layout corresponds to a layout of a standard cell whose connectivity is described by a netlist. For example, the netlist specifies net types for respective vias of the standard cell. One or more connectivity rings are formed within the design layout to provide connectivity for one or more vias of the design layout. For example, a first connectivity ring is generated, such as from mandrel, to connect one or more ring one vias. A second connectivity ring is generated, such as from passive pattern, to connect one or more ring two vias. One or more cuts are generated within the design layout to isolate vias having different net types. In this way, the design layout is self-aligned double patterning (SADP) compliant.

Abstract: An antenna includes a radiating element with a shape substantially conforming to a quadrilateral, a grounding and feed-in element, substantially surrounding the radiating element and having an opening formed near to a fourth side of the radiating element, wherein the grounding and feed-in element is electrically connected to a ground at one side of the opening and is electrically connected to a signal feed-in terminal at another side of the opening, a first connection element, having a terminal electrically connected to a first side and the fourth side of the radiating element, and another terminal electrically connected to the grounding and feed-in element, and a second connection element, having a terminal electrically connected to a third side and the fourth side of the radiating element, and another terminal electrically connected to the grounding and feed-in element.