Abstract: Computing devices are often designed in view of a particular usage scenario, but may be unsuitable for usage in other computing scenarios. For example, a notebook computer with a large display, an integrated keyboard, and a high-performance processor suitable for many computing tasks may be heavy, large, and power-inefficient; and a tablet lacking a keyboard and incorporating a low-powered processor may improve portability but may present inadequate performance for many tasks. Presented herein is a configuration of a computing device featuring a display unit with a resource-conserving processor that may be used independently (e.g., as a tablet), but that may be connected to a base unit featuring a resource-intensive processor. The operating system of the device may accordingly transition between a resource-intensive computing environment and a resource-conserving computing environment based on the connection with the base unit, thereby satisfying the dual roles of workstation and portable tablet device.

Abstract: Among other things, one or more techniques and systems for layout re-decomposition of a new layout corresponding to a change order to an original layout associated with an integrated circuit are provided. The change order is applied to the original layout to create the new layout. The original layout comprises one or more original pattern portions assigned pattern colors that correspond to pattern masks. One or more new pattern portions within the new layout are assigned pattern colors such that the new layout has a relatively high color similarity with respect to the original layout. In this way, changes to the pattern masks are reduced, thus mitigating fabrication delay or costs that would otherwise result from significant changes to the pattern masks.

Abstract: The present disclosure relates to a method of forming a reusable cut mask or trim mask that can be used for multiple design levels, and an associated apparatus. In some embodiments, the method is performed by determining positions of a plurality of mask cuts for a reusable cut mask or a reusable trim mask. Shapes are then routed along a routing path having a plurality of design levels. The routing path intersects one or more of the plurality of mask cuts at positions that form distinct shapes that connect nodes of an integrated chip sharing a same electric network. By routing shapes on a plurality of design levels to intersect one or more of the plurality of mask cuts, the cut masks can be reused between the plurality of levels, therefore decreasing mask costs during fabrication.

Abstract: A compound circuit board for a radar device includes a first substrate including a plurality of trace layers having a first trace layer formed with a digital signal processing unit and an electronic control unit in a first area, a second substrate including a plurality of trace layers having a second trace layer formed with an antenna module in a second area, and a prepreg layer between the first and second substrates for connecting the first and second substrates, wherein the first area and the second area in a first projecting result generated by projecting the first trace layer on the second trace layer are substantially overlapped.

Abstract: Systems, methods, and devices are described for implementing learning algorithms on data sets. A data set may be partitioned into a plurality of data partitions that may be distributed to two or more processors, such as a graphics processing unit. The data partitions may be processed in parallel by each of the processors to determine local counts associated with the data partitions. The local counts may then be aggregated to form a global count that reflects the local counts for the data set. The partitioning may be performed by a data partition algorithm and the processing and the aggregating may be performed by a parallel collapsed Gibbs sampling (CGS) algorithm and/or a parallel collapsed variational Bayesian (CVB) algorithm. In addition, the CGS and/or the CVB algorithms may be associated with the data partition algorithm and may be parallelized to train a latent Dirichlet allocation model.

Abstract: A receptacle connector (100) includes a housing (10), a front contact module (30) and a rear contact module (20) assembled in the housing. The housing has a cavity (12) opening along a horizontal direction. The cavity has a top wall (121) and a bottom wall (122) opposing to each other, the bottom wall having a tongue portion (120) at a front side of the housing. The rear contact module has a first contacts (22) and a second contacts (23) positioned on the top wall and the bottom wall respectively. The front contact module includes a one-piece insulator (31) assembled to a bottom side (13) of the housing, and a number of third contacts (32) insert-molded with the insulator.

Abstract: Among other things, one or more techniques and/or systems for performing design layout are provided. In an example, a design layout corresponds to a layout of a standard cell whose connectivity is described by a netlist. For example, the netlist specifies net types for respective vias of the standard cell. One or more connectivity rings are formed within the design layout to provide connectivity for one or more vias of the design layout. For example, a first connectivity ring is generated, such as from mandrel, to connect one or more ring one vias. A second connectivity ring is generated, such as from passive pattern, to connect one or more ring two vias. One or more cuts are generated within the design layout to isolate vias having different net types. In this way, the design layout is self-aligned double patterning (SADP) compliant.

Abstract: The present invention relates to electrically conductive polymer compositions, and their use in electronic devices. The compositions are an aqueous dispersion including: (i) at least one electrically conductive polymer doped with a non-fluorinated polymeric acid; (ii) at least one highly-fluorinated acid polymer; (iii) at least one water-compatible high-boiling organic solvent; and (iv) electrically insulative inorganic oxide nanoparticles.

Abstract: Some embodiments of the present disclosure relates to a method and apparatus to achieve a layout that is compatible with a multiple-patterning process. Two or more unit cells are constructed with layouts which satisfy the properties of the multiple-patterning process, and are each decomposed into two or more colors to support the multiple-patterning process. An active layout feature is merged with a dummy wire at a shared boundary between two unit cells. In the event of a short between two active layout features at the shared boundary, an automatic post-layout method can rearrange the layout features in a vicinity of the shared boundary to separate the active layout features to achieve cell functionality while satisfying the multiple-patterning properties.

Abstract: The present disclosure relates to a method of forming a reusable cut mask or trim mask that can be used for multiple design levels, and an associated apparatus. In some embodiments, the method is performed by determining positions of a plurality of mask cuts for a reusable cut mask or a reusable trim mask. Shapes are then routed along a routing path having a plurality of design levels. The routing path intersects one or more of the plurality of mask cuts at positions that form distinct shapes that connect nodes of an integrated chip sharing a same electric network. By routing shapes on a plurality of design levels to intersect one or more of the plurality of mask cuts, the cut masks can be reused between the plurality of levels, therefore decreasing mask costs during fabrication.

Abstract: A system and method of determining a cell layout are disclosed. The method includes receiving a circuit design corresponding to a predetermined circuit design, the circuit design having a first set of cells and abutting adjacent cells in the first set of cells, the abutted cells having a first boundary pattern therebetween. The first boundary pattern is exchanged with a second boundary pattern based on a number or positions of signal wires in the first boundary pattern. A cell layout for use in a patterning process can then be determined, the cell layout including the second boundary pattern.

Abstract: A method includes patterning a layer over a substrate with a first metal pattern; using a cut mask in a first position relative to the substrate to perform a first cut patterning for removing material from a first region within the first pattern; and using the same cut mask to perform a second cut patterning while in a second position relative to the same layer over the substrate, for removing material from a second region in a second metal pattern of the same layer over the substrate.

Abstract: A method identifies, as an independent node, any node representing a circuit pattern in any odd loop of a layout of a region of a layer of an IC that is not included in any other odd loop of the layout. The layer is to have a plurality of circuit patterns to be patterned using at least three photomasks. The method identifies, as a safe independent node, any independent node not closer than a threshold distance from any other independent nodes in another odd loop of the layout. The layout is modified, if the circuit patterns in the layout include any odd loop without any safe independent node, so that that after the modifying, each odd loop has at least one safe independent node.

Abstract: Among other things, one or more techniques and/or systems for performing design layout are provided. In an example, a design layout corresponds to a layout of a standard cell whose connectivity is described by a netlist. For example, the netlist specifies net types for respective vias of the standard cell. One or more connectivity rings are formed within the design layout to provide connectivity for one or more vias of the design layout. For example, a first connectivity ring is generated, such as from mandrel, to connect one or more ring one vias. A second connectivity ring is generated, such as from passive pattern, to connect one or more ring two vias. One or more cuts are generated within the design layout to isolate vias having different net types. In this way, the design layout is self-aligned double patterning (SADP) compliant.

Abstract: Among other things, one or more techniques and systems for performing design layout are provided. An initial design layout is associated with an electrical component, such as a standard cell. The initial design layout comprises a first pattern, such as a mandrel pattern, and a second pattern, such as a passive fill pattern. An initial cut pattern is generated for the initial design layout. Responsive to identifying a design rule violation associated with the initial cut pattern, the initial design layout is modified to generate a modified initial design layout. An updated cut pattern, not resulting in the design rule violation, is generated based upon the modified initial design layout. The updated cut pattern is applied to the modified initial design layout to generate a final design layout. The final design layout can be verified as self-aligned multiple patterning (SAMP) compliant.

Abstract: A radio-frequency transceiver system comprises a radio-frequency processing unit, a transmitting microwave network and a receiving microwave network, wherein the transmitting microwave network comprises a transmitting power divider for distributing main power of transmitting signals to two central sub-array antennas of four sub-array antennas, and the receiving microwave network comprises a receiving power divider for providing power mainly from a first input terminal and a second input terminal for a receiving route, and providing power mainly from the second input terminal and a third input terminal for another receiving route.

Abstract: Compositions are provided comprising a continuous liquid aqueous medium having dispersed therein a polydioxythiophene and at least one colloid-forming fluorinated polymeric acid. Films from invention compositions are useful as buffer layers in organic electronic devices, including electroluminescent devices, such as, for example, organic light emitting diodes (OLED) displays.

Abstract: The present invention relates to buffer bilayers, and their use in electronic devices. The bilayer has a first layer including (i) at least one electrically conductive polymer doped with at least one non-fluorinated polymeric acid and (ii) at least one highly-fluorinated acid polymer. The bilayer has a second layer which is a reacted layer from a metal which can be one or more transition metals, Group 13 metals, Group 14 metals, or lanthanide metals.

Abstract: The present invention relates to buffer bilayers, and their use in electronic devices. The bilayer has a first layer including at least one electrically conductive polymer doped with at least one highly-fluorinated acid polymer. The second layer is a reacted layer from a metal which can be one or more transition metals, Group 13 metals, Group 14 metals, or lanthanide metals.

Abstract: Compositions are provided comprising aqueous dispersions of at least one polypyrrole and at least one colloid-forming polymeric acid. The colloid-forming polymeric acid may be fluorinated. The new compositions are useful in electronic devices including organic electronic devices such as organic light emitting diode displays, memory storage, electromagnetic shielding, electrochromic displays, and thin film transistors, field effect resistance devices.