Abstract: A semiconductor device according to the present disclosure includes a first isolation feature and a second isolation feature, a fin structure extending lengthwise along a first direction and sandwiched between the first isolation feature and the second isolation feature along a second direction perpendicular to the first direction, a first channel member disposed over the first isolation feature, a second channel member disposed over the second isolation feature, and a gate structure disposed over and wrapping around the first channel member and the second channel member.

Abstract: A semiconductor structure includes a first semiconductor fin and a second semiconductor fin adjacent to the first semiconductor fin. The first and the second semiconductor fins extend lengthwise along a first direction over a substrate. A metal gate structure is disposed over the first and second semiconductor fins, the metal gate structure extending lengthwise along a second direction perpendicular to the first direction. A first epitaxial source/drain (S/D) feature is disposed over the first semiconductor fin, and a second epitaxial S/D feature is disposed over the second semiconductor fin. An interlayer dielectric (ILD) layer is disposed over the first and the second epitaxial S/D features. And an S/D contact is disposed directly above the first and second epitaxial S/D features. The S/D contact directly contacts the first epitaxial S/D feature, and the S/D contact is isolated from the second epitaxial S/D feature by the ILD layer.

Abstract: The present disclosure describes an inner spacer structure for a semiconductor device and a method for forming the same. The method for forming the inner spacer structure in the semiconductor device can include forming a vertical structure over a substrate, forming a gate structure over a portion of the vertical structure, exposing sidewalls of the portion of the vertical structure, forming multiple spacers over the sidewalls of the portion of the vertical structure, and forming a void in each of the multiple spacers.

Abstract: A method for estimating at least one electrical property of a semiconductor device is provided. The method includes forming the semiconductor device and at least one testing unit on a substrate, irradiating the testing unit with at least one electron beam, estimating electrons from the testing unit induced by the electron beam, and estimating the electrical property of the semiconductor device according to intensity of the estimated electrons from the testing unit.

Abstract: An integrated circuit includes a first and second active region, a first conductive structure, an insulating region, a set of gates and a set of contacts. The first and second active region are in a substrate, extend in a first direction, are located on a first level, and being separated from one another in a second direction. The first conductive structure extends in the first direction, is located on the first level, and is between the first and second active region. The insulating region is located on at least the first level, and is between the first and second active region and the first conductive structure. The set of gates extend in the second direction, overlap the first conductive structure, and is located on a second level. The set of contacts extend in the second direction, overlap the first conductive structure, and is located on the second level.

Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first epitaxial structure and a second epitaxial structure spaced apart from the first epitaxial structure. The semiconductor device structure also includes a conductive contact electrically connected to the first epitaxial structure and a first conductive via over the conductive contact. The semiconductor device structure further includes a second conductive via directly above the second epitaxial structure. The second conductive via is longer than the first conductive via.

Abstract: A method for an electronic device in a power mode change operation, an electronic device, and a communication system are provided. In an embodiment, the method comprises the following steps. During the power mode change operation, the electronic device detects whether a power mode change failure occurs in the electronic device after transmitting a power mode change request frame. The electronic device transmits the first burst ending signal to notify another electronic device of the power mode change failure in the electronic device, wherein the first burst ending signal indicates burst closure and includes a first error indication signal to indicate the power mode change failure in the electronic device. Thus, in response to the first burst ending signal, the other electronic device can abort a power mode configuration to avoid undesirable un-synchronous states.

Abstract: Method for facilitating data link layer initialization and an electronic device are provided. The method comprises following operations during data link layer initialization in an electronic device. A first acknowledgment and flow control (AFC) frame is transmitted to another electronic device, the first AFC frame including a first indicator to notify the other electronic device that the electronic device does not receive any AFC frame. It is determined that an AFC frame is received within a first time interval after the first AFC frame is transmitted, the first time interval being less than an expiration value of a protection timer. In response to the received AFC frame, a second AFC frame is transmitted to the other electronic device, the second AFC frame including a second indicator to notify the other electronic device that the electronic device receives an AFC frame from the other electronic device.

Abstract: A display device includes a circuit substrate and first to third light-emitting elements. The circuit substrate has first to third sub-pixels. Each of the first to third sub-pixels has a first bonding area and a second bonding area. The first light-emitting element is located in the first bonding area of the first sub-pixel, and is bonded to the circuit substrate through a first solder structure. The second light-emitting element is located in the second sub-pixel. There is first residual solder on the first bonding area of the second sub-pixel. The third light-emitting element is located on one of the first bonding area and the second bonding area of the third sub-pixel, and is bonded to the circuit substrate through a conductive adhesive structure.

Abstract: A semiconductor device is provided. The semiconductor device includes a silicon layer over a fin, a doped semiconductor layer over the fin and adjoining the silicon layer, a plurality of channel layers over the silicon layer, a source/drain structure on the doped semiconductor layer and adjoining plurality of channel layers, and a plurality of inner spacers between the plurality of channel layers.

Abstract: Provided are a microstructured optical film structure with a latitude position optimization function applicable to a solar light-collection module installed (operated) in a direction perpendicular (orthogonal) to sunlight or a direction perpendicular (orthogonal) to the ground and a method of using the light-collection film to collect sunlight or ambient light. The microstructured optical film structure includes a solar (PV) module. The module is applicable to various inorganic/organic photovoltaic chips/photoelectric sensors/modules thereof and includes optimized microstructured optical film layers capable of receiving different light rays incident at various angles from different latitude spaces.

Abstract: A semiconductor structure includes a first semiconductor fin and a second semiconductor fin adjacent to the first semiconductor fin. The first and the second semiconductor fins extend lengthwise along a first direction over a substrate. A metal gate structure is disposed over the first and second semiconductor fins, the metal gate structure extending lengthwise along a second direction perpendicular to the first direction. A first epitaxial source/drain (S/D) feature is disposed over the first semiconductor fin, and a second epitaxial S/D feature is disposed over the second semiconductor fin. An interlayer dielectric (ILD) layer is disposed over the first and the second epitaxial S/D features. And an S/D contact is disposed directly above the first and second epitaxial S/D features. The S/D contact directly contacts the first epitaxial S/D feature, and the S/D contact is isolated from the second epitaxial S/D feature by the ILD layer.

Abstract: Disclosed are examples related to PCB impedance tuning for wideband operation and acceptance of antenna variation. In one example, a tire monitoring device includes a sensor, RFID circuitry and processing circuitry mounted on a PCB. The RFID circuitry can harvest energy and transmit monitored tire data in response to a received interrogation signal. The RFID circuitry can be tuned to receive interrogation signals in a frequency band from at least 868 MHz to at least 915 MHz to cover both NA and EU applications. Impedance matching of the RFID circuitry can enable operation independent of variations in coil antenna length. In another example, comprises the tire monitoring device and a RFID reader or interrogator.

Abstract: A display panel including a circuit substrate, first display sub-pixels and a repaired display sub-pixel is provided. The first display sub-pixel includes a light-emitting device and a first color conversion pattern. The light-emitting device is disposed on the circuit substrate, and is suitable for emitting first light with a first light-emitting color. The first color conversion pattern is arranged on the light-emitting device, and overlaps the light-emitting device. The first color conversion pattern is suitable for converting the first light-emitting color of the first light into a first color. The first color is different from the first light-emitting color. The repaired display sub-pixel includes a repair light-emitting device arranged on the circuit substrate, and having a second light-emitting color. The second light-emitting color is the same as the first color. A method of fabricating the display panel is also provided.

Abstract: A semiconductor device is provided. The semiconductor device includes a plurality of channel layers stacked over a semiconductor substrate and spaced apart from one another, a source/drain structure adjoining the plurality of channel layers, a gate structure wrapping around the plurality of channel layers, and a first inner spacer between the gate structure and the source/drain structure and between the plurality of channel layers. The first inner spacer is made of an oxide of a semiconductor material.

Abstract: A device includes an active region, a gate structure, a source/drain epitaxial structure, an epitaxial layer, a metal alloy layer, a contact, and a contact etch stop layer. The gate structure is across the active region. The source/drain epitaxial structure is over the active region and adjacent the gate structure. The epitaxial layer is over the source/drain epitaxial structure. The metal alloy layer is over the epitaxial layer. The contact is over the metal alloy layer. The contact etch stop layer lines sidewalls of the source/drain epitaxial structure. The metal alloy layer is spaced apart from the contact etch stop layer.

Abstract: A semiconductor structure includes a fin disposed on a substrate, the fin including a channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein. The semiconductor structure further includes a gate stack engaging the channel region of the fin and gate spacers disposed between the gate stack and the source and drain regions of the fin, wherein each channel of the channels includes a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers, wherein a concentration of germanium in the middle section of the channel is higher than a concentration of germanium in the two end sections of the channel, and wherein the middle section of the channel further includes a core portion and an outer portion surrounding the core portion with a germanium concentration profile from the core portion to the outer portion.

Abstract: A synchronization circuit for an interconnection protocol, a controller and a storage device are provided. The synchronization circuit includes a first synchronization circuit module and a second synchronization circuit module. The first synchronization circuit module converts first control information of a first clock domain output by a data link layer receiver of the first device into second control information of a second clock domain, and outputs the second control information of the second clock domain. The second synchronization circuit module is coupled to the first synchronization circuit module, and converts the second control information of the second clock domain output by the first synchronization circuit module into third control information of a third clock domain to be output to a data link layer transmitter of the first device. Any two among the first, second and third clock domains are asynchronous.