Patents by Inventor Hsuan Chang

Hsuan Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230036175
    Abstract: Methods of spatially directing the orientation and placement of multiple block copolymer (BCP) domains on isolated regions of a substrate are described. The methods involve epitaxially directing the assembly of BCP domains using spatial boundaries between regions with different surface composition, formed at the edges of isolated chemical regions on a background chemistry. Multiple vertical domains of BCP order on the isolated region, self-aligned in a direction parallel to edges of the isolated region. In some embodiments, vertical domains order on multiple isolated regions of a first chemistry of a chemical contrast pattern with horizontal domains on the regions of a second (background) chemistry of the chemical contrast pattern. Also provided herein are compositions resulting from the methods.
    Type: Application
    Filed: December 22, 2020
    Publication date: February 2, 2023
    Inventors: Michael Arnold, Robert Jacobberger, Paul F. Nealey, Shisheng Xiong, Tzu-Hsuan Chang, Zhenqiang Ma
  • Patent number: 11569380
    Abstract: A semiconductor structure is provided, and the semiconductor structure includes a substrate, and an active area is defined thereon, a gate structure spanning the active area, wherein the overlapping range of the gate structure and the active area is defined as an overlapping region, and the overlapping region includes four corners, and at least one salicide block covering the four corners of the overlapping region.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: January 31, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Hsuan Chang, Ming-Hua Tsai, Chin-Chia Kuo
  • Publication number: 20230027674
    Abstract: A semiconductor device and method for manufacturing the same are provided. The method includes providing a first substrate. The method also includes forming a first metal layer on the first substrate. The first metal layer includes a first metal material. The method further includes treating a first surface of the first metal layer with a solution including an ion of a second metal material. In addition, the method includes forming a plurality of metal particles including the second metal material on a portion of the first surface of the first metal layer.
    Type: Application
    Filed: September 30, 2022
    Publication date: January 26, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jhao-Cheng CHEN, Huang-Hsien CHANG, Wen-Long LU, Shao Hsuan CHUANG, Ching-Ju CHEN, Tse-Chuan CHOU
  • Patent number: 11559164
    Abstract: Disclosures of the present invention describe a coaxial microwave rotary applicator for material processing, mainly comprising: a waveguide unit, a microwave generator connected to one end of the waveguide unit, a bearing unit, a chamber, a rotary shaft, a driver unit, a sampling unit. The bearing unit is connected to the waveguide unit through a non-rotary ring, and the chamber is connected to a rotary ring of the bearing unit, and the microwave generator is configured for supplying a microwave to the chamber. By such arrangements, it is able to uniformly heat a specific material disposed in the chamber by driving the chamber to rotate. It is worth noting that, a user is allowed to clearly observe the processing progress via the sampling unit during the heating process of the specific material.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: January 24, 2023
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Hsein-Wen Chao, Tsun-Hsu Chang, Huan-Jun Guo, Cheng-Hsuan Chan, Po-Yen Chiu, Yu-Tzu Chang
  • Patent number: 11555842
    Abstract: A system, a method and a built-in phase noise measurement apparatus are introduced. The built-in phase noise measurement apparatus includes a first DLL and a TDC, in which the first DLL circuit controls a delay of a first signal to generate a second signal based on a control code, tune the control code until a phase of the second signal is aligned to a phase of a reference clock signal, and record a value of the control code when the phase of the second signal is aligned to the phase of the reference clock signal. The DLL circuit controls the delay of the first signal based on the value of the control code after the phase of the second signal is aligned to the phase of the reference clock signal. The TDC determines the phase noise of the first signal based on the reference clock signal and the second signal.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: January 17, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mao-Hsuan Chou, Chih-Hsien Chang, Ruey-Bin Sheen, Ya-Tin Chang
  • Patent number: 11555851
    Abstract: An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (??) time-to-digital converter (TDC) are disclosed. In some embodiments, an apparatus includes a plurality of first-order ?? TDCs formed in an integrated circuit (IC) chip, wherein each of the first-order ?? TDCs are connected to one another in a MASH type configuration to provide the MASH type high-order ?? TDC, wherein the MASH type high-order ?? TDC is configured to measure the phase noise of a device under text (DUT).
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: January 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mao-Hsuan Chou, Ya-Tin Chang, Ruey-Bin Sheen, Chih-Hsien Chang
  • Publication number: 20230007939
    Abstract: A method for a clean procedure during manufacturing a semiconductor device, includes: providing a patterned sacrificial gate structure including a gate dielectric and a sacrificial layer; wherein the patterned sacrificial gate structure is embedded in a dielectric layer and an upper surface of the sacrificial layer is exposed; performing a first etching process to remove the sacrificial layer; and performing a hydrophilic treatment and a hydrophobic treatment to remove a residue of the sacrificial layer.
    Type: Application
    Filed: August 2, 2021
    Publication date: January 12, 2023
    Inventors: Chuan-Chang WU, Zhen WU, Hsuan-Hsu CHEN, Chun-Lung CHEN
  • Publication number: 20230008005
    Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.
    Type: Application
    Filed: July 28, 2022
    Publication date: January 12, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Ju Chou, Chih-Chung Chang, Jiun-Ming Kuo, Che-Yuan Hsu, Pei-Ling Gao, Chen-Hsuan Liao
  • Publication number: 20230006062
    Abstract: A semiconductor structure is provided, and the semiconductor structure includes a substrate, and an active area is defined thereon, a gate structure spanning the active area, wherein the overlapping range of the gate structure and the active area is defined as an overlapping region, and the overlapping region includes four corners, and at least one salicide block covering the four corners of the overlapping region.
    Type: Application
    Filed: July 2, 2021
    Publication date: January 5, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Hsuan Chang, Ming-Hua Tsai, Chin-Chia Kuo
  • Patent number: 11545447
    Abstract: A semiconductor device includes a substrate, a first isolation structure, a second isolation structure and a dummy pattern. The substrate includes a first part surrounding a second part at a top view. The first isolation structure is disposed between the first part and the second part, to isolate the first part from the second part. The second isolation structure is disposed at at least one corner of the first part. The dummy pattern is disposed on the second isolation structure. The present invention also provides a method of forming said semiconductor device.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: January 3, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Hsuan Chang, Ming-Hua Tsai, Chin-Chia Kuo
  • Publication number: 20220411992
    Abstract: A manufacturing method for an antibacterial fiber includes the following steps. A dipping step is performed to soak a conductive fiber in a solution, in which the solution includes an ionic compound, and the ionic compound includes a metal cation. An oxidation step is performed by using the conductive fiber as an anode, such that an antibacterial material produced by the solution is adhered to a surface of the conductive fiber, in which the antibacterial material includes a metal oxide.
    Type: Application
    Filed: June 29, 2022
    Publication date: December 29, 2022
    Applicant: FORMOSA PLASTICS CORPORATRION
    Inventors: Chih-Hsiang LIANG, Yu-Cheng HSU, Tang-Chun KAO, Chien-Hsu CHOU, Yi-Chuan CHANG, Chih-Hsuan OU, Han-Chang WU, Long-Tyan HWANG
  • Publication number: 20220411804
    Abstract: The present invention relates to PIKFYVE antisense oligonucleotides (ASOs), pharmaceutical compositions containing them, and methods for treating, inhibiting, suppressing, and preventing neurological diseases with them.
    Type: Application
    Filed: June 22, 2022
    Publication date: December 29, 2022
    Inventors: Wen-Hsuan Chang, Emily Elizabeth Lee
  • Patent number: 11538805
    Abstract: A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: December 27, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Chang Chiu, Chia-Ching Lee, Chien-Hao Chen, Hung-Chin Chung, Hsien-Ming Lee, Chi On Chui, Hsuan-Yu Tung, Chung-Chiang Wu
  • Publication number: 20220403042
    Abstract: Disclosed herein are humanized antibodies, antigen-binding fragments thereof, and antibody conjugates, that are capable of specifically binding to certain biantennary Lewis antigens, which antigens are expressed in a variety of cancers. The presently disclosed antibodies are useful to target antigen-expressing cells for treatment or detection of disease, including various cancers. Also provided are polynucleotides, vectors, and host cells for producing the disclosed antibodies and antigen-binding fragments thereof. Pharmaceutical compositions, methods of treatment and detection, and uses of the antibodies, antigen-binding fragments, antibody conjugates, and compositions are also provided.
    Type: Application
    Filed: July 26, 2022
    Publication date: December 22, 2022
    Inventors: Tong-Hsuan CHANG, Mei-Chun YANG, Liahng-Yirn LIU, Jerry TING, Shu-Yen CHANG, Yen-Ying CHEN, Yu-Yu LIN, Shu-Lun TANG
  • Publication number: 20220406707
    Abstract: A method is provided for producing a semiconductor structure including at least one capacitor. The method includes: forming a first metal layer; forming a second metal layer; forming a third high resistance (HiR) layer interposed between the first metal layer and the second metal layer, wherein at least one of the first metal layer and the sconed metal layer at least partially overlap with the third HiR layer; and defining at least one of a first capacitor between the first metal layer and the third HiR layer and a second capacitor between the second metal layer and the third HiR layer. Suitably, the method is carried out subsequent to a front-end-of-line (FEOL) portion of a semiconductor fabrication process.
    Type: Application
    Filed: February 9, 2022
    Publication date: December 22, 2022
    Inventors: Mingni Chang, Hsuan-Ming Huang, Shiou-Fan Chen
  • Publication number: 20220406085
    Abstract: A driving apparatus and an operation method thereof are provided. The driving apparatus includes a first driving circuit and a second driving circuit. The first driving circuit suspends performing at least one of a display driving operation and a touch sensing operation during a skip period under a driving mode, and the first driving circuit performs the at least one of the display driving operation and the touch sensing operation outside the skip period under the driving mode. The second driving circuit is coupled to the first driving circuit. The second driving circuit performs a fingerprint sensing operation during the skip period.
    Type: Application
    Filed: August 19, 2022
    Publication date: December 22, 2022
    Applicant: Novatek Microelectronics Corp.
    Inventors: Wei-Lun Shih, Tsen-Wei Chang, Cho-Hsuan Jhang, Chih-Peng Hsia, Cheng-Yu Chiang
  • Patent number: 11532514
    Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a conductive feature over a semiconductor substrate and forming a dielectric layer over the conductive feature. The method also includes forming an opening in the dielectric layer to expose the conductive feature. The method further includes forming a conductive material to overfill the opening. In addition, the method includes thinning the conductive material using a chemical mechanical polishing process. A slurry used in the chemical mechanical polishing process includes an iron-containing oxidizer that oxidizes a portion of the conductive material.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Chieh Wu, Kuo-Hsiu Wei, Kei-Wei Chen, Tang-Kuei Chang, Chia Hsuan Lee, Jian-Ci Lin
  • Patent number: 11531380
    Abstract: An electronic device including two bodies and at least one hinge structure is provided. The hinge structure includes a first bracket, a second bracket, a first rotation component, and a second rotation component. The hinge structure is connected to the two bodies via the first bracket and the second bracket respectively. The first rotation component is connected rotatably to the first bracket by taking a first axis as a rotation axis. The second rotation component is connected rotatably to the first rotation component by taking the first axis as a rotation axis, and is connected rotatably to the second bracket by taking a second axis as a rotation axis, wherein the first axis and the second axis are parallel to each other.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: December 20, 2022
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Cheng-Ya Chi, Chien-Chu Chen, Ken-Ping Lin, Cheng-Shiue Jan, Yao-Lin Chang, Han-Hsuan Tsai, Jui-Min Huang, Chih-Wen Chiang
  • Patent number: 11532718
    Abstract: A semiconductor device includes a substrate, a plurality of insulators, a liner structure and a gate stack. The substrate has fins and trenches in between the fins. The insulators are disposed within the trenches of the substrate. The liner structure is disposed on the plurality of insulators and across the fins, wherein the liner structure comprises sidewall portions and a cap portion, the sidewall portions is covering sidewalls of the fins, the cap portion is covering a top surface of the fins and joined with the sidewall portions, and a maximum thickness T1 of the cap portion is greater than a thickness T2 of the sidewall portions. The gate stack is disposed on the liner structure and across the fins.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hsuan Liao, Chih-Chung Chang, Chun-Heng Chen, Jiun-Ming Kuo
  • Patent number: D977385
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: February 7, 2023
    Assignee: ABILITY OPTO-ELECTRONICS TECHNOLOGY CO. LTD.
    Inventors: Yeong-Ming Chang, Yi-Chi Cheng, Tzu-Hsuan Wei, Chien-Hsun Lai, Yao-Wei Liu