Patents by Inventor Hsuan Lee

Hsuan Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230215761
    Abstract: A memory device includes first transistor over a semiconductor substrate, wherein the first transistor includes a first word line extending over the semiconductor substrate; a second transistor over the semiconductor substrate, wherein the second transistor includes a second word line extending over the first word line; a first air gap extending between the first word line and the second word line; a memory film extending along and contacting the first word line and the second word line; a channel layer extending along the memory film; a source line extending along the channel layer, wherein the memory film is between the source line and the word line; a bit line extending along the channel layer, wherein the memory film is between the bit line and the word line; and an isolation region between the source line and the bit line.
    Type: Application
    Filed: March 6, 2023
    Publication date: July 6, 2023
    Inventors: Sheng-Chen Wang, Kai-Hsuan Lee, Sai-Hooi Yeong, Chia-Ta Yu, Han-Jong Chia
  • Patent number: 11694825
    Abstract: A radial-leaded over-current protection device comprises a PTC element, a first electrode lead, a second electrode lead and an electrically insulating encapsulation layer. The PTC element comprises a first conductive layer, a second conductive layer and a PTC material layer laminated therebetween. The PTC material layer comprises crystalline polymer and conductive filler dispersed therein. The first electrode lead has an end connecting to the first conductive layer, whereas the second electrode lead has an end connecting to the second conductive layer. The electrically insulating encapsulation layer includes a fluorine-containing polymer, and wraps around an entire outer surface of the PTC element and the ends of the first and second electrodes connecting to the PTC element. The electrically insulating encapsulation layer has a thickness of 102˜105 nm, and the radial-leaded over-current protection device has an initial resistance Rbf of 0.0017˜0.0027?.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: July 4, 2023
    Assignee: POLYTRONICS TECHNOLOGY CORP.
    Inventors: Feng Ji Li, Yi-Hsuan Lee, Yung Hsien Chang
  • Patent number: 11688607
    Abstract: The present disclosure provides a slurry. The slurry includes an abrasive including a ceria compound; a removal rate regulator to adjust removal rates of the slurry to metal and to dielectric material; and a buffering agent to adjust a pH value of the slurry, wherein the slurry comprises a dielectric material removal rate higher than a metal oxide removal rate.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: June 27, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Hung Liao, Chung-Wei Hsu, Tsung-Ling Tsai, Chen-Hao Wu, An-Hsuan Lee, Shen-Nan Lee, Teng-Chun Tsai, Huang-Lin Chao
  • Publication number: 20230190202
    Abstract: An electrophysiological signal measurement system, an electrophysiological signal adjustment method and an electrode assembly are provided. The electrophysiological signal measurement system includes an electrode assembly, a variation adjustment device and a signal processing device. The electrode assembly receives an electrophysiological signal, a first electrical characteristic value and a second electrical characteristic value. The variation adjustment device includes a comparison unit and a searching unit. The comparison unit receives the first electrical characteristic value and the second electrical characteristic value, and determines whether a difference between the first electrical characteristic value and the second electrical characteristic value is greater than a threshold.
    Type: Application
    Filed: March 16, 2022
    Publication date: June 22, 2023
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Heng-Yin CHEN, Yun-Yi HUANG, Min-Hsuan LEE, Yi-Cheng LU, Yu-Chiao TSAI, Bor-Shyh LIN
  • Patent number: 11682675
    Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate, the gate structure being surrounded by a first interlayer dielectric (ILD) layer; forming a trench in the first ILD layer adjacent to the fin; filling the trench with a first dummy material; forming a second ILD layer over the first ILD layer and the first dummy material; forming an opening in the first ILD layer and the second ILD layer, the opening exposing a sidewall of the first dummy material; lining sidewalls of the opening with a second dummy material; after the lining, forming a conductive material in the opening; after forming the conductive material, removing the first and the second dummy materials from the trench and the opening, respectively; and after the removing, sealing the opening and the trench by forming a dielectric layer over the second ILD layer.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: June 20, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Hsuan Lee, Sai-Hooi Yeong, Chi On Chui
  • Patent number: 11682571
    Abstract: Apparatus and methods for handling die carriers are disclosed. In one example, a disclosed apparatus includes: a load port configured to load a die carrier operable to hold a plurality of dies into a processing tool; and a lane changer coupled to the load port and configured to move at least one die in the die carrier to an input of the processing tool and transfer the at least one die into the processing tool for processing the at least one die.
    Type: Grant
    Filed: June 24, 2022
    Date of Patent: June 20, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Sheng Kuo, Kai-Chieh Huang, Wei-Ting Hsiao, Yang-Ann Chu, I-Lun Yang, Hsuan Lee
  • Publication number: 20230166891
    Abstract: A locking mechanism for container and lid thereof may include a container and a lid, and the peripheral edge of the upper opening of the container has a first periphery edge. At least two first coupling portions, which are located at symmetric positions, and at least two second coupling portions, which are located at symmetric positions, outwardly protrude from the first periphery edge respectively. The lid comprises a second peripheral edge at the outer periphery thereof, and the inner surface of the second peripheral edge is configured to couple with and cover the first peripheral edge of the container. At least two first connecting portions respectively protrude from the second peripheral edge at symmetric positions, and at least two second connecting portions, which are located at symmetric positions, outwardly protrude from the second periphery edge respectively.
    Type: Application
    Filed: November 26, 2021
    Publication date: June 1, 2023
    Inventor: CHEN-HSUAN LEE
  • Publication number: 20230170234
    Abstract: A die sorter tool may include a first conveyor, and a first lane to receive, from one or more load ports and via the first conveyor, a carrier with a set of dies. The die sorter tool may include a die flip module to receive the carrier from the first lane, manipulate one or more dies of the set of dies by changing orientations of the one or more dies, and return the one or more dies to the carrier after manipulating the one or more dies and without changing positions of the one or more dies within the carrier. The die sorter tool may include a second conveyor, and a second lane to receive, via the second conveyor, the carrier from the die flip module, and provide, via the first conveyor, the carrier to the one or more load ports.
    Type: Application
    Filed: January 30, 2023
    Publication date: June 1, 2023
    Inventors: Chih-Hung HUANG, Cheng-Lung WU, Zheng-Lin HE, Yang-Ann CHU, Jiun-Rong PAI, Hsuan LEE
  • Patent number: 11663690
    Abstract: A video processing method includes: decoding apart of a bitstream to generate a decoded frame, where the decoded frame is a projection-based frame that includes projection faces in a projection layout; and remapping sample locations of the projection-based frame to locations on the sphere, where a sample location within the projection-based frame is converted into a local sample location within a projection face packed in the projection-based frame; in response to adjustment criteria being met, an adjusted local sample location within the projection face is generated by applying adjustment to at least one coordinate value of the local sample location within the projection face, and the adjusted local sample location within the projection face is remapped to a location on the sphere; and in response to the adjustment criteria not being met, the local sample location within the projection face is remapped to a location on the sphere.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: May 30, 2023
    Assignee: MEDIATEK INC.
    Inventors: Ya-Hsuan Lee, Jian-Liang Lin
  • Patent number: 11659206
    Abstract: A video decoding method includes: decoding a part of a bitstream to generate a decoded frame, and parsing at least one syntax element from the bitstream. The decoded frame is a projection-based frame that includes projection faces packed in a cube-based projection layout. At least a portion of a 360-degree content of a sphere is mapped to the projection faces via cube-based projection. The at least one syntax element is indicative of a guard band configuration of the projection-based frame.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: May 23, 2023
    Assignee: MEDIATEK INC.
    Inventors: Ya-Hsuan Lee, Jian-Liang Lin
  • Patent number: 11651984
    Abstract: A multiple transport carrier docking device may be capable of storing and/or staging a plurality of transport carriers in a chamber of the multiple transport carrier docking device, and may be capable of forming an air-tight seal around a transport carrier in the chamber. Semiconductor wafers in the transport carrier may be accessed by a wafer transport tool while the air-tight seal around the transport carrier prevents and/or reduces the likelihood that contaminants in the semiconductor fabrication facility will reach the semiconductor wafers. The air-tight seal around the transport carrier may reduce defects of the semiconductor wafers that might otherwise be caused by the contaminants, may increase manufacturing yield and quality in the semiconductor fabrication facility, and/or may permit the continued reduction in device and/or feature sizes of integrated circuits and/or semiconductor devices that are to be formed on semiconductor wafers.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: May 16, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hung Huang, Cheng-Lung Wu, Yang-Ann Chu, Hsuan Lee, Jiun-Rong Pai
  • Publication number: 20230121958
    Abstract: Interconnect structures exhibiting reduced accumulation of copper vacancies along interfaces between contact etch stop layers (CESLs) and interconnects, along with methods for fabrication, are disclosed herein. A method includes forming a copper interconnect in a dielectric layer and depositing a metal nitride CESL over the copper interconnect and the dielectric layer. An interface between the metal nitride CESL and the copper interconnect has a first surface nitrogen concentration, a first nitrogen concentration and/or a first number of nitrogen-nitrogen bonds. A nitrogen plasma treatment is performed to modify the interface between the metal nitride CESL and the copper interconnect.
    Type: Application
    Filed: December 20, 2022
    Publication date: April 20, 2023
    Inventors: Hui Lee, Po-Hsiang Huang, Wen-Sheh Huang, Jen Hung Wang, Su-Jen Sung, Chih-Chien Chi, Pei-Hsuan Lee
  • Publication number: 20230123292
    Abstract: A method of manufacturing a FinFET includes at last the following steps. A semiconductor substrate is patterned to form trenches in the semiconductor substrate and semiconductor fins located between two adjacent trenches of the trenches. Gate stacks is formed over portions of the semiconductor fins. Strained material portions are formed over the semiconductor fins revealed by the gate stacks. First metal contacts are formed over the gate stacks, the first metal contacts electrically connecting the strained material portions. Air gaps are formed in the FinFET at positions between two adjacent gate stacks and between two adjacent strained materials.
    Type: Application
    Filed: December 13, 2022
    Publication date: April 20, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sai-Hooi Yeong, Kai-Hsuan Lee, Yu-Ming Lin, Chi-On Chui
  • Publication number: 20230123863
    Abstract: The present invention comprises a system and method for co-culturing glia cells and neurons in a combination of glia culture medium and neuron medium wherein the glia cells and neurons have cell morphology, cell reactions and/or cell interactions that exist in vivo after the co-culturing for up to about 21 days, up to about 30 days, up to about 40 days, up to about 45 days. Since the cell morphology, cell reaction and/or cell interaction of the co-culture are similar to those seen in vivo, the present system is capable of being configured as animal models for research, drug screening, testing and conducting clinical trials.
    Type: Application
    Filed: June 30, 2020
    Publication date: April 20, 2023
    Inventors: Yi-Hsuan Lee, Chia-Chi Hung, Pei-Chien Hsu, Yu-Jie Huang
  • Patent number: 11626220
    Abstract: A surface-mountable over-current protection device comprises at least one PTC material layer, a first conductive layer, a second conductive layer, a first electrode, a second electrode, an insulating layer, and a cover layer. The PTC material layer comprises crystalline polymer and conductive fillers dispersed therein. The first conductive layer and the second conductive layer are disposed on a first surface and a second surface of the PTC material layer, respectively. The first electrode and the second electrode are electrically connected to the first conductive layer and the second conductive layer, respectively. The insulating layer is disposed between the first electrode and the second electrode for insulation. The cover layer includes a fluorine-containing polymer, and wraps around an entire outer surface of the surface-mountable over-current protection device.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: April 11, 2023
    Assignee: POLYTRONICS TECHNOLOGY CORP.
    Inventors: Feng Ji Li, Yi-Hsuan Lee, Yung Hsien Chang
  • Publication number: 20230103560
    Abstract: In an embodiment, a device includes: a package component including: integrated circuit dies; an encapsulant around the integrated circuit dies; a redistribution structure over the encapsulant and the integrated circuit dies, the redistribution structure being electrically coupled to the integrated circuit dies; sockets over the redistribution structure, the sockets being electrically coupled to the redistribution structure; and a support ring over the redistribution structure and surrounding the sockets, the support ring being disposed along outermost edges of the redistribution structure, the support ring at least partially laterally overlapping the redistribution structure.
    Type: Application
    Filed: November 14, 2022
    Publication date: April 6, 2023
    Inventors: Shu-Rong Chun, Kuo Lung Pan, Tin-Hao Kuo, Hao-Yi Tsai, Pei-Hsuan Lee, Chien Ling Hwang, Yu-Chia Lai, Po-Yuan Teng, Chen-Hua Yu
  • Publication number: 20230095609
    Abstract: A system, includes, a semiconductor processing unit, an Automated Materials Handling System (AMHS) vehicle, and a warehouse apparatus, wherein the warehouse apparatus comprises at least one input port, at least one output port, and at least one load/unload port, wherein the warehouse apparatus is configured to perform one of the following: receiving a plurality of tray cassette containers from the AMHS vehicle at the at least one input port, transporting at least one tray cassette in each of a plurality of tray cassette containers to the at least one load/unload port via the at least one input port, transporting at least one first tray from the at least one tray cassette to the semiconductor processing unit via a tray feeder conveyor, and receiving at least one second tray from the semiconductor processing unit via the tray feeder conveyor.
    Type: Application
    Filed: December 2, 2022
    Publication date: March 30, 2023
    Inventors: Tsung-Sheng Kuo, Yang-Ann Chu, Chih-Hung Huang, Guan-Wei Huang, Jiun-Rong Pai, Hsuan Lee
  • Patent number: 11610841
    Abstract: Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the conductive line. A second dielectric layer disposed over the conductive line and a third dielectric layer disposed over the first dielectric layer. A via extends through the second dielectric layer and is coupled to the conductive line. The second dielectric layer and the third dielectric layer are coplanar and the second and third dielectric layers have a different composition. In some embodiments, the second dielectric layer is selectively deposited on the conductive line.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: March 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ta Yu, Kai-Hsuan Lee, Yen-Ming Chen, Chi On Chui, Sai-Hooi Yeong
  • Publication number: 20230082564
    Abstract: A coupled physiological signal measurement method, a coupled physiological signal measurement system and a graphic user interface are provided. The coupled physiological signal measurement method includes the following steps. An original myoelectric signal is captured. A capacitance value of a skin is obtained. The original myoelectric signal is compensated according to the capacitance value of the skin. The step of compensating the original myoelectric signal according to the capacitance value includes the following steps. The original myoelectric signal is decomposed to obtain several myoelectric sub-signals corresponding to several frequencies, wherein each myoelectric sub-signal has an amplitude variation. The amplitude variations of the myoelectric sub-signals are respectively adjusted according to the capacitance value of the skin. The adjusted myoelectric sub-signals are merged to obtain a compensated myoelectric signal.
    Type: Application
    Filed: January 27, 2022
    Publication date: March 16, 2023
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Heng-Yin CHEN, Yun-Yi HUANG, Min-Hsuan LEE, Yu-Chiao TSAI
  • Publication number: 20230085231
    Abstract: The present disclosure proposes an electromagnetic susceptibility (EMS) testing method based on computer-vision. The method includes a training stage and a testing stage. During the training stage, the electronic device receives a testing data and the monitor displays a first picture. A camera captures the first picture to generate a template video. The processor generates a plurality of template images at least according to the template video. During the testing stage, an antenna emits an interference signal to the electronic device. The electronic device receives the testing data and the monitor displays a second picture. The camera captures the second picture to generate a testing video. The processor generates a testing image according to the testing video and calculates a difference ratio between the testing image and each template image. The processor sends an alert signal when the difference ratio is greater than a threshold.
    Type: Application
    Filed: December 13, 2021
    Publication date: March 16, 2023
    Inventors: Trista Pei-Chun CHEN, HAO HSUAN LEE, LI TE KO, MING-FENG LEE, CHIH CHANG CHEN, Hsin-Hung Lin