Patents by Inventor Hsuan Lee

Hsuan Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Materials and methods for chemical mechanical polishing of ruthenium-containing materials
    Patent number: 11525072
    Abstract: A chemical mechanical polishing (CMP) slurry composition includes an oxidant including oxygen, and an abrasive particle having a core structure encapsulated by a shell structure. The core structure includes a first compound and the shell structure includes a second compound different from the first compound, where a diameter of the core structure is greater than a thickness of the shell structure, and where the first compound is configured to react with the oxidant to form a reactive oxygen species.
    Type: Grant
    Filed: February 15, 2021
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: An-Hsuan Lee, Shen-Nan Lee, Chen-Hao Wu, Chun-Hung Liao, Teng-Chun Tsai, Huang-Lin Chao
  • Systems and methods for tray cassette warehousing
    Patent number: 11527425
    Abstract: A system, includes, a semiconductor processing unit, an Automated Materials Handling System (AMHS) vehicle, and a warehouse apparatus, wherein the warehouse apparatus comprises at least one input port, at least one output port, and at least one load/unload port, wherein the warehouse apparatus is configured to perform one of the following: receiving a plurality of tray cassette containers from the AMHS vehicle at the at least one input port, transporting at least one tray cassette in each of a plurality of tray cassette containers to the at least one load/unload port via the at least one input port, transporting at least one first tray from the at least one tray cassette to the semiconductor processing unit via a tray feeder conveyor, and receiving at least one second tray from the semiconductor processing unit via the tray feeder conveyor.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: December 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Sheng Kuo, Yang-Ann Chu, Chih-Hung Huang, Guan-Wei Huang, Jiun-Rong Pai, Hsuan Lee
  • BIFUNCTIONAL FILM
    Publication number: 20220388293
    Abstract: A method for preparing a bifunctional film, including: (a) drying a first polymer solution to form a film to form an anti-adhesion layer, and (b) drying a second polymer solution over the anti-adhesion layer to form a film to form an attachment layer. The first polymer solution includes a first hydrophobic solution and a first hydrophilic solution, and in the first polymer solution, the weight ratio of the solute of the first hydrophobic solution to the solute of the first hydrophilic solution is 1:0.01-1. Moreover, the second polymer solution is composed of a second hydrophilic solution.
    Type: Application
    Filed: August 11, 2022
    Publication date: December 8, 2022
    Applicant: Industrial Technology Research Institute
    Inventors: Hsin-Hsin SHEN, Yu-Chi WANG, Ming-Chia YANG, Yu-Bing LIOU, Wei-Hong CHANG, Yun-Han LIN, Hsin-Yi HSU, Yun-Chung TENG, Chia-Jung LU, Yi-Hsuan LEE, Jian-Wei LIN, Kun-Mao KUO, Ching-Mei CHEN
  • AIR GAP FORMATION BETWEEN GATE SPACER AND EPITAXY STRUCTURE
    Publication number: 20220384442
    Abstract: A semiconductor device includes a gate stack, an epitaxy structure, a first spacer, a second spacer, and a dielectric residue. The gate stack is over a substrate. The epitaxy structure is formed raised above the substrate. The first spacer is on a sidewall of the gate stack. The first spacer and the epitaxy structure define a void therebetween. The second spacer seals the void between the first spacer and the epitaxy structure. The dielectric residue is in the void and has an upper portion and a lower portion under the upper portion. The upper portion of the dielectric residue has a silicon-to-nitrogen atomic ratio higher than a silicon-to-nitrogen atomic ratio of the lower portion of the dielectric residue.
    Type: Application
    Filed: August 10, 2022
    Publication date: December 1, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bo-Yu LAI, Kai-Hsuan LEE, Wei-Yang LEE, Feng-Cheng YANG, Yen-Ming CHEN
  • Methods of Forming an Abrasive Slurry and Methods for Chemical-Mechanical Polishing
    Publication number: 20220384245
    Abstract: Methods of forming a slurry and methods of performing a chemical mechanical polishing (CMP) process utilized in manufacturing semiconductor devices, as described herein, may be performed on semiconductor devices including integrated contact structures with ruthenium (Ru) plug contacts down to a semiconductor substrate. The slurry may be formed by mixing a first abrasive, a second abrasive, and a reactant with a solvent. The first abrasive may include a first particulate including titanium dioxide (TiO2) particles and the second abrasive may include a second particulate that is different from the first particulate. The slurry may be used in a CMP process for removing ruthenium (Ru) materials and dielectric materials from a surface of a workpiece resulting in better WiD loading and planarization of the surface for a flat profile.
    Type: Application
    Filed: August 5, 2022
    Publication date: December 1, 2022
    Inventors: Chia Hsuan Lee, Chun-Wei Hsu, Chia-Wei Ho, Chi-Hsiang Shen, Li-Chieh Wu, Jian-Ci Lin, Chi-Jen Liu, Yi-Sheng Lin, Yang-Chun Cheng, Liang-Guang Chen, Kuo-Hsiu Wei, Kei-Wei Chen
  • SYSTEMS AND METHODS FOR DIE TRANSFER
    Publication number: 20220384222
    Abstract: In certain embodiments, a system includes: a source lane configured to move a first die container between a load port and a source lane staging area; an inspection sensor configured to produce a sensor result based on a die on the first die container; a pass target lane configured to move a second die container between a pass target lane out port and a pass target lane staging area; a fail target lane configured to move a third die container between a fail target lane out port and a fail target lane staging area; and a conveyor configured to move the die from the first die container at the source lane staging area to either the second die container at the pass target lane staging area or the fail target lane staging area based on the sensor result.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: Tsung-Sheng KUO, Chih-Hung HUANG, Yi-Fam SHIU, Chueng-Jen WANG, Hsuan LEE, Jiun-Rong PAI
  • Support for multi-type users in a single-type computing system
    Patent number: 11516307
    Abstract: Persistent storage contains a parent table and one or more child tables, the parent table containing: a class field specifying types, and one or more filter fields. One or more processors may: receive a first request to read first information of a first type for a first entity; determine that, in a first entry of the parent table for the first entity, the first type is specified in the class field; obtain the first information from a child table associated with the first type; receive a second request to read second information of a second type for a second entity; determine that, in a second entry of the parent table for the second entity, the second type is indicated as present by a filter field that is associated with the second type; and obtain the second information from a set of additional fields in the second entry.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: November 29, 2022
    Assignee: ServiceNow, Inc.
    Inventors: Vincent Seguin, Patrick Casey, David Schumann, Szu-hsuan Lee
  • Sealed reticle storage device with soft contact
    Patent number: 11511920
    Abstract: The invention discloses a reticle storage device including a top lid, a bottom lid and a soft contact member. The top lid has a ceiling and a cover surrounding the ceiling. The bottom lid has a carrier and a peripheral structure surrounding the carrier. The soft contact member is configured to laterally extend in between the cover and the peripheral structure when the top lid and the bottom lid engage with each other, and to extend from an inside to an outside of the device in order to buffer the contact among the two lids.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: November 29, 2022
    Assignee: GUDENG PRECISION INDUSTRIAL CO., LTD.
    Inventors: Chia-Ho Chuang, Hsin-Min Hsueh, Yi-Hsuan Lee, Hsing-Min Wen, Ming-Chien Chiu
  • Apparatus and methods for automatically handling die carriers
    Patent number: 11508596
    Abstract: Apparatus and methods for automatically handling die carriers are disclosed. In one example, a disclosed apparatus includes: at least one load port each configured for loading a die carrier operable to hold a plurality of dies; and an interface tool coupled to the at least one load port and a semiconductor processing unit. The interface tool comprises: a first robotic arm configured for transporting the die carrier from the at least one load port to the interface tool, and a second robotic arm configured for transporting the die carrier from the interface tool to the semiconductor processing unit for processing at least one die in the die carrier.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: November 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Sheng Kuo, Cheng-Lung Wu, Chih-Hung Huang, Yang-Ann Chu, Hsuan Lee, Jiun-Rong Pai
  • PACKAGE SYSTEM AND MANUFACTURING METHOD THEREOF
    Publication number: 20220367310
    Abstract: A package system and a manufacturing method thereof are provided. The package system includes a semiconductor package and a thermal-dissipating structure. The semiconductor package includes a first surface and a second surface opposing to each other, and a planarity of the second surface is greater than that of the first surface. The thermal-dissipating structure includes a first plate secured to the semiconductor package, a gasket interposed between the first plate and the semiconductor package, a second plate secured to the semiconductor package opposite to the first plate, and a first thermal interface material layer interposed between the second plate and the second surface of the semiconductor package. The gasket includes a plurality of hollow regions corresponding to portions of the first surface of the semiconductor package.
    Type: Application
    Filed: May 13, 2021
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Hsuan Lee, Ching-Hua Hsieh, Chien-Ling Hwang
  • Engaging structure of a container and its cover
    Publication number: 20220363449
    Abstract: An engaging structure for a container and its cover has a containing body and a corresponding covering member. The upper opening of the containing body has an outer lip edge, the opposing positions of the outer lip edge is provided with at least two the engaging portions. The outer edge of the engaging portion has with a movable buckle, the outer periphery of the covering member is provided with a covering lip covering the outer lip edge of the containing body, and the opposing positions of the periphery of the covering lip has at least two the locking portions corresponding to the engaging portion of the containing body. A locking protrusion is disposed on the locking portion, locking portion of the covering member is corresponding to each engaging portion of the containing body. By flipping the movable buckle, each the engaging curve can be fastened tightly to each locking protrusions.
    Type: Application
    Filed: March 28, 2022
    Publication date: November 17, 2022
    Inventor: CHEN-HSUAN LEE
  • SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20220367623
    Abstract: A semiconductor device structure includes nanostructures formed over a substrate. The structure also includes a gate structure formed over and around the nanostructures. The structure also includes a spacer layer formed over a sidewall of the gate structure over the nanostructures. The structure also includes a source/drain epitaxial structure formed adjacent to the spacer layer. The structure also includes a contact structure formed over the source/drain epitaxial structure with an air spacer formed between the spacer layer and the contact structure.
    Type: Application
    Filed: November 19, 2021
    Publication date: November 17, 2022
    Inventors: Kai-Hsuan Lee, Shih-Che Lin, Po-Yu Huang, Shih-Chieh Wu, I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Integrated circuit package and method
    Patent number: 11502013
    Abstract: In an embodiment, a device includes: a package component including: integrated circuit dies; an encapsulant around the integrated circuit dies; a redistribution structure over the encapsulant and the integrated circuit dies, the redistribution structure being electrically coupled to the integrated circuit dies; sockets over the redistribution structure, the sockets being electrically coupled to the redistribution structure; and a support ring over the redistribution structure and surrounding the sockets, the support ring being disposed along outermost edges of the redistribution structure, the support ring at least partially laterally overlapping the redistribution structure.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Rong Chun, Kuo Lung Pan, Tin-Hao Kuo, Hao-Yi Tsai, Pei-Hsuan Lee, Chien Ling Hwang, Yu-Chia Lai, Po-Yuan Teng, Chen-Hua Yu
  • Systems and methods for linking metric data to resources
    Patent number: 11500874
    Abstract: The present approach relates generally to systems and methods for outputting metric data from resources with a database accessible by a client instance. The client instance is hosted by one or more data centers and accessible by one or more remote client networks. In accordance with the present approach, a request to track metric data related to a resource is received. Further, a configuration item (CI) is retrieved from a database accessible by the client instance based at least in part on data associated with the request. Further, a type of CI is identified. Even further, a resource type associated with the type of the CI is identified based at least in part on a resource abstraction layer accessible by the client instance. Further still, the resource type is linked to the resource table and metric data associated with the resource is outputted.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: November 15, 2022
    Assignee: ServiceNow, Inc.
    Inventors: Ritika Goyal, Szu-hsuan Lee, Vincent Seguin, Kanwaldeep Kaur Dang, Anand Nikhil Mehta
  • Battery charging method employing historical data
    Patent number: 11502529
    Abstract: A battery charging method is disclosed. The method includes: obtaining historical working durations in which the electronic device was powered by a battery of the electronic device; in response to an electronic device connected to a charging power source, obtaining a remaining battery level and a target capacity of a battery of the electronic device, and accordingly defining a capacity to be charged; obtaining a current system time when the electronic device is connected to the charging power source; obtaining a specific time difference between the current system time and a predicted working duration, wherein the predicted working duration is a specific working duration chosen from the historical working durations subsequent to the current system time; and using the capacity to be charged to correspond to the specific time difference to obtain a predicted charging current value.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: November 15, 2022
    Assignee: PEGATRON CORPORATION
    Inventors: Shih-Feng Tseng, Yi-Hsuan Lee, Wen-Lin Huang
  • FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20220359683
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and a first inter-layer dielectric (ILD) layer formed over the fin structure. The FinFET device structure includes a gate structure formed in the first ILD layer, and a first S/D contact structure formed in the first ILD layer and adjacent to the gate structure. The FinFET device structure also includes a first air gap formed on a sidewall of the first S/D contact structure, and the first air gap is in direct contact with the first ILD layer.
    Type: Application
    Filed: May 6, 2021
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Hsuan LEE, I-Wen WU, Chen-Ming LEE, Jian-Hao CHEN, Fu-Kai YANG, Feng-Cheng YANG, Mei-Yun WANG, Yen-Ming CHEN
  • Integrated Circuit Package and Method
    Publication number: 20220359344
    Abstract: In an embodiment, a device includes: a package component including integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure over the encapsulant and the integrated circuit dies, and sockets over the redistribution structure; a mechanical brace physically coupled to the sockets, the mechanical brace having openings, each one of the openings exposing a respective one of the sockets; a thermal module physically and thermally coupled to the encapsulant and the integrated circuit dies; and bolts extending through the thermal module, the mechanical brace, and the package component.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 10, 2022
    Inventors: Shu-Rong Chun, Kuo-Lung Pan, Pei-Hsuan Lee, Chien Ling Hwang, Yu-Chia Lai, Tin-Hao Kuo, Hao-Yi Tsai, Chen-Hua Yu
  • PACKAGE STRUCTURE
    Publication number: 20220359343
    Abstract: A package structure includes a bottom plate, a semiconductor package, a top plate, a screw and an anti-loosening coating. The semiconductor package is disposed over the bottom plate. The top plate is disposed over the semiconductor package, and includes an internal thread in a screw hole of the top plate. The screw penetrates through the bottom plate, the semiconductor package and the top plate, and includes an external thread. The external thread of the screw is engaged to the internal thread of the top plate, and the anti-loosening coating is adhered between the external thread and the internal thread.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chia Lai, Chen-Hua Yu, Chung-Shi Liu, Hsiao-Chung Liang, Hao-Yi Tsai, Chien-Ling Hwang, Kuo-Lung Pan, Pei-Hsuan Lee, Tin-Hao Kuo, Chih-Hsuan Tai
  • FINFET DEVICE AND METHOD
    Publication number: 20220359755
    Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Inventors: Su-Hao Liu, Kuo-Ju Chen, Kai-Hsuan Lee, I-Hsieh Wong, Cheng-Yu Yang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Syun-Ming Jiang, Meng-Han Chou
  • Method and apparatus for reducing artifacts in projection-based frame
    Patent number: 11494870
    Abstract: An exemplary video processing method includes: receiving an omnidirectional content corresponding to a sphere; obtaining a plurality of projection faces from the omnidirectional content of the sphere according to a pyramid projection; creating at least one padding region; and generating a projection-based frame by packing the projection faces and the at least one padding region in a pyramid projection layout. The projection faces packed in the pyramid projection layout include a first projection face. The at least one padding region packed in the pyramid projection layout includes a first padding region. The first padding region connects with at least the first projection face, and forms at least a portion of one boundary of the pyramid projection layout.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: November 8, 2022
    Assignee: MEDIATEK INC.
    Inventors: Jian-Liang Lin, Peng Wang, Ya-Hsuan Lee, Hung-Chih Lin, Shen-Kai Chang