Abstract: A keyboard file verification method based on image processing comprises controlling a processor to perform following operations: obtaining a keyboard file; generating, according to the keyboard file, a search index and a feature image; obtaining a template image from a template database according to the search index; performing a calibration operation according to the feature image, wherein the calibration operation comprises: adjusting a resolution of the feature image according to a resolution of the template image; performing a shifting operation according to the feature image, to generate a plurality of candidate images; and comparing a key block of each of the plurality of candidate images with a key block of the template image to generate a difference map and a comparison result.

Abstract: A memory device includes first transistor over a semiconductor substrate, wherein the first transistor includes a first word line extending over the semiconductor substrate; a second transistor over the semiconductor substrate, wherein the second transistor includes a second word line extending over the first word line; a first air gap extending between the first word line and the second word line; a memory film extending along and contacting the first word line and the second word line; a channel layer extending along the memory film; a source line extending along the channel layer, wherein the memory film is between the source line and the word line; a bit line extending along the channel layer, wherein the memory film is between the bit line and the word line; and an isolation region between the source line and the bit line.

Abstract: Apparatus and methods for automatically handling die carriers are disclosed. In one example, a disclosed apparatus includes: at least one load port each configured for loading a die carrier operable to hold a plurality of dies; and an interface tool coupled to the at least one load port and a semiconductor processing unit. The interface tool comprises: a first robotic arm configured for transporting the die carrier from the at least one load port to the interface tool, and a second robotic arm configured for transporting the die carrier from the interface tool to the semiconductor processing unit for processing at least one die in the die carrier.

Abstract: A device includes a semiconductor substrate; a word line extending over the semiconductor substrate; a memory film extending along the word line, wherein the memory film contacts the word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; source lines extending along the memory film, wherein the memory film is between the source lines and the word line; bit lines extending along the memory film, wherein the memory film is between the bit lines and the word line; and isolation regions, wherein each isolation region is between a source line and a bit line, wherein each of the isolation regions includes an air gap and a seal extending over the air gap.

Abstract: A method includes forming a gate structure on a substrate, forming a seal spacer covering a sidewall of the gate structure, forming a sacrificial spacer covering a sidewall of the seal spacer, forming source/drain regions sandwiching a channel region that is under the gate structure, and depositing a contact etch stop layer covering a sidewall of the sacrificial spacer. The method further includes removing the sacrificial spacer to form a trench, wherein the trench exposes a sidewall of the contact etch stop layer and the sidewall of the seal spacer, and depositing an inter-layer dielectric layer, wherein the inter-layer dielectric layer caps the trench, thereby defining an air gap inside the trench.

Abstract: The method includes receiving a semiconductor device having a first surface and a second surface. The first surface is a top surface including a conductive material exposed thereon; and the second surface is an embedded surface including the conductive material and a dielectric material. The method also includes selecting a first polishing slurry to achieve a first polishing rate of the conductive material in the first polishing slurry and a second polishing rate of the dielectric material in the first polishing slurry. The method further includes selecting a second polishing slurry to achieve a third polishing rate of the conductive material in the second polishing slurry and a fourth polishing rate of the dielectric material in the second polishing slurry. The method additionally includes polishing the first surface with the first polishing slurry until the second surface is exposed; and polishing the second surface with the second polishing slurry.

Abstract: Persistent storage contains a parent table and one or more child tables, the parent table containing: a class field specifying types, and one or more filter fields. One or more processors may: receive a first request to read first information of a first type for a first entity; determine that, in a first entry of the parent table for the first entity, the first type is specified in the class field; obtain the first information from a child table associated with the first type; receive a second request to read second information of a second type for a second entity; determine that, in a second entry of the parent table for the second entity, the second type is indicated as present by a filter field that is associated with the second type; and obtain the second information from a set of additional fields in the second entry.

Abstract: Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes receiving a fin-shaped structure comprising a first channel region and a second channel region, a first and a second dummy gate structures disposed over the first and the second channel regions, respectively. The method also includes removing a portion of the first dummy gate structure, a portion of the first channel region and a portion of the substrate under the first dummy gate structure to form a trench, forming a hybrid dielectric feature in the trench, removing a portion of the hybrid dielectric feature to form an air gap, sealing the air gap, and replacing the second dummy gate structure with a gate stack after sealing the air gap.

Abstract: A surge protection system is provided. The surge protection system includes an input capacitor, a surge protection circuit, and a controller. When the input voltage starts to be transmitted to the input capacitor, a surge current is generated. The surge protection circuit includes a first path and a second path. The surge protection circuit is coupled to a second end of the input capacitor via the first path, so that the surge current is transmitted via the first path. The controller is coupled to the surge protection circuit. The controller is configured to provide a control signal to the surge protection circuit to switch the first path to the second path to be coupled to the second end of the input capacitor.

Abstract: Disclosed in embodiments of the present disclosure are a communication terminal, a communication system and an audio information processing method, the communication terminal includes a sound reception assembly and a basic communication module, wherein the basic communication module of the communication terminal receives second pickup audio information in a wireless manner, such that the communication terminal acquires returned audio information according to first pickup audio information generated by the communication terminal and the received second pickup audio information, and transmits outwards the returned audio information. Therefore, the technical solution in the embodiments of the present disclosure may realize synchronous sound reception of a plurality of wireless sound reception apparatuses or wireless sound reception components, and may satisfy a requirement for multiple people to use, thereby achieving a good sound reception effect.

Abstract: A die sorter tool may include a first conveyor, and a first lane to receive, from one or more load ports and via the first conveyor, a carrier with a set of dies. The die sorter tool may include a die flip module to receive the carrier from the first lane, manipulate one or more dies of the set of dies by changing orientations of the one or more dies, and return the one or more dies to the carrier after manipulating the one or more dies and without changing positions of the one or more dies within the carrier. The die sorter tool may include a second conveyor, and a second lane to receive, via the second conveyor, the carrier from the die flip module, and provide, via the first conveyor, the carrier to the one or more load ports.

Abstract: The present disclosure describes a method and an apparatus that can enhance the slurry oxidizability for a chemical mechanical polishing (CMP) process. The method can include securing a substrate onto a carrier of a polishing system. The method can further include dispensing, via a feeder of the polishing system, a first slurry towards a polishing pad of the polishing system. The method can further include forming a second slurry by enhancing an oxidizability of the first slurry, and performing a polishing process, with the second slurry, on the substrate.

Abstract: A method of manufacturing a FinFET includes at last the following steps. A semiconductor substrate is patterned to form trenches in the semiconductor substrate and semiconductor fins located between two adjacent trenches of the trenches. Gate stacks is formed over portions of the semiconductor fins. Strained material portions are formed over the semiconductor fins revealed by the gate stacks. First metal contacts are formed over the gate stacks, the first metal contacts electrically connecting the strained material portions. Air gaps are formed in the FinFET at positions between two adjacent gate stacks and between two adjacent strained materials.

Abstract: A method includes depositing an interlayer dielectric (ILD) over a source/drain region, implanting impurities into a portion of the ILD, recessing the portion of the ILD to form a trench, forming spacers on sidewalls of the trench, the spacers including a spacer material, forming a source/drain contact in the trench and removing the spacers and the portion of the ILD with an etching process to form an air-gap, the air-gap disposed under and along sidewalls of the source/drain contact, where the etching process selectively etches the spacer material and the impurity.

Abstract: A wireless communication terminal including a wireless transceiver and a controller is provided. The wireless transceiver performs wireless transmission and reception to and from an Access Point (AP). The controller is coupled to the wireless transceiver, and configures the wireless communication terminal to operate as a Station (STA) to associate with the AP in compliance with an Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard. Also, the controller receives a beacon frame indicating to disable an UL MU operation from the AP via the wireless transceiver, and enables the STA to operate in a contention mode for UL transmission in response to receiving the beacon frame indicating to disable the UL MU operation.

Abstract: In an embodiment, a device includes: a package component including integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure over the encapsulant and the integrated circuit dies, and sockets over the redistribution structure; a mechanical brace physically coupled to the sockets, the mechanical brace having openings, each one of the openings exposing a respective one of the sockets; a thermal module physically and thermally coupled to the encapsulant and the integrated circuit dies; and bolts extending through the thermal module, the mechanical brace, and the package component.

Abstract: Interconnect structures exhibiting reduced accumulation of copper vacancies along interfaces between contact etch stop layers (CESLs) and interconnects, along with methods for fabrication, are disclosed herein. A method includes forming a copper interconnect in a dielectric layer and depositing a metal nitride CESL over the copper interconnect and the dielectric layer. An interface between the metal nitride CESL and the copper interconnect has a first surface nitrogen concentration, a first nitrogen concentration and/or a first number of nitrogen-nitrogen bonds. A nitrogen plasma treatment is performed to modify the interface between the metal nitride CESL and the copper interconnect.

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a conductive feature over a semiconductor substrate and forming a dielectric layer over the conductive feature. The method also includes forming an opening in the dielectric layer to expose the conductive feature. The method further includes forming a conductive material to overfill the opening. In addition, the method includes thinning the conductive material using a chemical mechanical polishing process. A slurry used in the chemical mechanical polishing process includes an iron-containing oxidizer that oxidizes a portion of the conductive material.

Abstract: A surface-mountable over-current protection device comprises at least one PTC material layer, a first conductive layer, a second conductive layer, a first electrode, a second electrode, an insulating layer, and a cover layer. The PTC material layer comprises crystalline polymer and conductive fillers dispersed therein. The first conductive layer and the second conductive layer are disposed on a first surface and a second surface of the PTC material layer, respectively. The first electrode and the second electrode are electrically connected to the first conductive layer and the second conductive layer, respectively. The insulating layer is disposed between the first electrode and the second electrode for insulation. The cover layer includes a fluorine-containing polymer, and wraps around an entire outer surface of the surface-mountable over-current protection device.

Abstract: A radial-leaded over-current protection device comprises a PTC element, a first electrode lead, a second electrode lead and an electrically insulating encapsulation layer. The PTC element comprises a first conductive layer, a second conductive layer and a PTC material layer laminated therebetween. The PTC material layer comprises crystalline polymer and conductive filler dispersed therein. The first electrode lead has an end connecting to the first conductive layer, whereas the second electrode lead has an end connecting to the second conductive layer. The electrically insulating encapsulation layer includes a fluorine-containing polymer, and wraps around an entire outer surface of the PTC element and the ends of the first and second electrodes connecting to the PTC element. The electrically insulating encapsulation layer has a thickness of 102˜105 nm, and the radial-leaded over-current protection device has an initial resistance Rbf of 0.0017˜0.0027?.