Patents by Inventor Hsuan Lin

Hsuan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220372645
    Abstract: A method for creating colorful patterns on a metal surface by using colorless ink is revealed. First carry out a first anodizing process on a metal substrate to form a first anodic oxide layer on a surface of the metal substrate. Then coat a layer of colorless ink on the first anodic oxide layer on the surface of the metal substrate to form a colorless ink pattern mask. Later perform a second anodizing process to form a second anodic oxide layer on a part of the metal substrate without being covered with the colorless ink pattern mask. Next remove the colorless ink pattern mask and coat a metal film over the first anodic oxide layer and the second anodic oxide layer to get a colorful pattern on the metal substrate.
    Type: Application
    Filed: May 20, 2021
    Publication date: November 24, 2022
    Inventors: CHEN-KUEI CHUNG, CHIN-JOU KUO, WEI-HSUAN LIN
  • Patent number: 11504613
    Abstract: A game controller is provided. The game controller includes a first handle body. The first handle body includes a first control module, a first operation interface, a first connection portion and a second connection portion. The first connection portion is a male connector. The first handle body is connected to a mobile device through the first connection portion. The second connection portion is a female connector. The first handle body is connected to a second handle body through the second connection portion and a signal transmission wire. A first terminal and a second terminal of the signal transmission wire each includes a male connector.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: November 22, 2022
    Assignee: DEXIN CORPORATION
    Inventors: Ho-Lung Lu, Chin-Lung Lin, Hsiu-Hsuan Lin
  • Publication number: 20220366988
    Abstract: A content-address memory (CAM) and an operation method are provided. The content-address memory comprises: a plurality of first signal lines; a plurality of second signal lines; and a plurality of CAM memory cells coupled to the first signal lines and the second signal lines, wherein in data match, a plurality of input signals are input into the CAM memory cells via the first signal lines; the input signals are compared with contents stored in the CAM memory cells; and a match result is determined based on an electrical characteristic of the second signal lines.
    Type: Application
    Filed: May 14, 2021
    Publication date: November 17, 2022
    Inventors: Po-Hao TSENG, Yu-Hsuan LIN, Feng-Min LEE, Ming-Hsiu Lee
  • Publication number: 20220362348
    Abstract: The present invention provides a lactoferrin, a derived peptide thereof, a composition comprising the same and a use thereof for inhibiting and/or alleviating lipid synthesis. The lactoferrin comprises the amino acid sequence of SEQ ID NO: 01, and the derived peptide of the lactoferrin comprises at least one selected from the amino acid sequences of SEQ ID NO: 02, SEQ ID NO: 03, and SEQ ID NO: 04.
    Type: Application
    Filed: August 19, 2021
    Publication date: November 17, 2022
    Applicant: RENORIGIN INNOVATION INSTITUTE CO., LTD.
    Inventors: Hsiu-Chin HUANG, Hsuan LIN
  • Publication number: 20220369246
    Abstract: A method for improving transmission power management with compliance to regulations of radiofrequency exposure, which may comprise: at a current time, estimating whether a window average power, which may reflect average power transmitted using a radio technology during a moving time window, will exceed a power limit after the current time; if true, proceeding to at least one of a first handling subroutine and a second handling subroutine to set a power cap, and causing power transmitted to be capped by the power cap after the current time. The first handling subroutine may comprise: scheduling to set the power cap lower at a scheduled time. Estimating whether the window average power will exceed the power limit may involve discarding one of a plurality of power records. The second handling subroutine may comprise: setting the power cap not higher than the discarded one of the plurality of power records.
    Type: Application
    Filed: April 11, 2022
    Publication date: November 17, 2022
    Inventors: Yi-Hsuan LIN, Han-Chun CHANG, Chih-Yuan LIN, Yi-Ying HUANG
  • Publication number: 20220367269
    Abstract: The present disclosure provides embodiments of a semiconductor device. In one embodiment, the semiconductor device includes a gate structure, a source/drain feature adjacent the gate structure, a first dielectric layer over the source/drain feature, an etch stop layer over the gate structure and the first dielectric layer, a second dielectric layer over the etch stop layer, a source/drain contact that includes a first portion extending through the first dielectric layer and a second portion extending through the etch stop layer and the second dielectric layer, a metal silicide layer disposed between the second portion and etch stop layer, and a metal nitride layer disposed between the first portion and the first dielectric layer.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 17, 2022
    Inventors: Chih-Hsuan Lin, Xi-Zong Chen, Chih-Teng Liao
  • Publication number: 20220367667
    Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 17, 2022
    Inventors: Yu-Wen Cheng, Cheng-Tung Lin, Chih-Wei Chang, Hong-Mao Lee, Ming-Hsing Tsai, Sheng-Hsuan Lin, Wei-Jung Lin, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Wei-Yip Loh, Ya-Yi Cheng
  • Patent number: 11503739
    Abstract: An electronic apparatus with a cooling system includes a chassis having a mounting slot; a heat exchanger disposed in the chassis; a removable device is disposed in the mounting slot, and includes a housing and a first pump disposed in the housing; a tube is connected to the heat exchanger and the first pump and a sliding mechanism is disposed in the chassis, and connected to the tube. When the removable device is moved to a mounting location, the tube drives the sliding mechanism to a storage location. When the removable device is moved to a detachable location, the tube drives the sliding mechanism to an extension location, wherein the extension location is closer to the mounting slot than the storage location.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: November 15, 2022
    Assignee: Nanning FuLian FuGui Precision Industrial Co., Ltd.
    Inventor: Chih-Hsuan Lin
  • Publication number: 20220359016
    Abstract: A storage device for generating an identity code and an identity code generating method are disclosed. The storage device includes a first storage circuit, a second storage circuit and a reading circuit. The first storage circuit stores a plurality of first data and the first data have a plurality of bits. The second storage circuit stores a plurality of second data and the second data have a plurality of bits. The reading circuit reads the second data from the second storage circuit to form a first sequence, selects a first portion of the first data according to the first sequence, reads the first portion of the first data from the first storage circuit to form a target sequence and outputs the target sequence to serve as an identity code.
    Type: Application
    Filed: July 29, 2021
    Publication date: November 10, 2022
    Inventors: Yu-Hsuan LIN, Dai-Ying LEE, Ming-Hsiu LEE
  • Patent number: 11482717
    Abstract: A dehydrogenation method for hydrogen storage materials, which is executed by a fuel cell system. The fuel cell system includes a hydrogen storage material tank, a heating unit, a fuel cell, a pump, a water thermal management unit and a heat recovery unit. The described dehydrogenation method utilizes the heating unit and the heat recovery unit to provide thermal energy to the hydrogen storage material tank, so that hydrogen storage material is heated to the dehydrogenation temperature. The pump extracts hydrogen from the hydrogen storage material tank, so that the hydrogen storage material is under negative pressure (i.e. H2 absolute pressure below 1 atm), according to which the hydrogen storage material is dehydrogenated, and the dehydrogenation efficiency and the amount of hydrogen release are improved. The method n can reduce the dehydrogenation temperature of the hydrogen storage material, and reduce the thermal energy consumption for heating the hydrogen storage material.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: October 25, 2022
    Inventors: Chia-Chieh Shen, Shih-Hung Chan, Fang-Bor Weng, Ho Chun Cheung, Yi-Hsuan Lin, Mei-Chin Chen, Jyun-Wei Chen, Ya-Che Wu, Han-Wen Liu, Kuan-Lin Chen, Jin-Xun Zhang
  • Publication number: 20220334167
    Abstract: A method for detecting defects in a GaN high electron mobility transistor is disclosed. The method includes steps of measuring a plurality of electrical characteristics of a GaN high electron mobility transistor, measuring the plurality of electrical characteristics after performing a deterioration test on the GaN high electron mobility transistor, irradiating the GaN high electron mobility transistor in turns with a plurality of light sources with different wavelengths and measuring the plurality of electrical characteristics after each irradiation of the GaN high electron mobility transistor by each of the plurality of light sources, and comparing changes of the plurality of electrical characteristics measured in the above steps to determine the defect location of the GaN high electron mobility transistor.
    Type: Application
    Filed: June 10, 2021
    Publication date: October 20, 2022
    Inventors: Ting-Chang CHANG, Hao-Xuan ZHENG, Yu-Shan LIN, Fu-Yuan JIN, Fong-Min CIOU, Mao-Chou TAI, Yun-Hsuan LIN, Wei-Chen HUANG, Wen-Chung CHEN
  • Patent number: 11477364
    Abstract: A solid-state image sensor having a first region and a second region adjacent to the first region along a first direction is provided. The solid-state image sensor includes a first unit pattern disposed in the first region. The solid-state image sensor also includes a second unit pattern disposed in the second region and corresponding to the first unit pattern. The first unit pattern and the second unit pattern each includes normal pixels and an auto-focus pixel array. The normal pixels and the auto-focus pixel array in the first unit pattern form a first arrangement, the normal pixels and the auto-focus pixel array in the second unit pattern form a second arrangement, and the first arrangement and the second arrangement are symmetric with respect to the first axis of symmetry.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: October 18, 2022
    Assignee: VISERA TECHNOLOGIES COMPANY LIMITED
    Inventors: Cheng-Hsuan Lin, Zong-Ru Tu, Yu-Chi Chang, Han-Lin Wu, Hung-Jen Tsai
  • Patent number: 11476207
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate disposed on the semiconductor substrate. The semiconductor device structure also includes a source doped region and a drain doped region on two opposite sides of the gate. The semiconductor device structure further includes a source protective circuit and a drain protective circuit. From a side perspective view, a first drain conductive element of the source protective circuit partially overlaps a first source conductive element of the drain protective circuit.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: October 18, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Jian-Hsing Lee, Shao-Chang Huang, Chih-Hsuan Lin, Yu-Kai Wang, Karuna Nidhi, Hwa-Chyi Chiou
  • Publication number: 20220329447
    Abstract: A PoE system includes a plurality of PoE devices and a hub that are coupled in a ring configuration through a plurality of network cables. The hub is coupled to two of the network cables, and provides electric power to at least one of the network cables that is coupled to the hub. Each of the PoE devices is coupled to two of the network cables, receives electric power from one of the two network cables, and supplies electric power to the other one of the two network cables. As a consequence, each of the PoE devices can be directly or indirectly powered by the hub.
    Type: Application
    Filed: August 27, 2021
    Publication date: October 13, 2022
    Inventors: Jian-Jia WANG, Shih-Hsuan LIN, Li-Wei CHU, Li-Chun CHOU
  • Patent number: 11467758
    Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided. The method includes: receiving a first write command from a host system; selecting a first physical erasing unit from at least one physical erasing unit available for writing and writing data corresponding to the first write command to the first physical erasing unit by using a single page programming mode or a multi-page programming mode when the number of physical erasing units available for writing is greater than a first threshold; and selecting a second physical erasing unit from the at least one physical erasing unit available for writing and writing data corresponding to the first write command into the second physical erasing unit by only using the single page programming mode when the number of physical erasing units available for writing is not greater than the first threshold.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: October 11, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Chieh Yang, Yi-Hsuan Lin, Tai-Yuan Huang, Ping-Chuan Lin
  • Publication number: 20220321791
    Abstract: A solid-state image sensor having a first region and a second region adjacent to the first region along a first direction is provided. The solid-state image sensor includes a first unit pattern disposed in the first region. The solid-state image sensor also includes a second unit pattern disposed in the second region and corresponding to the first unit pattern. The first unit pattern and the second unit pattern each includes normal pixels and an auto-focus pixel array. The normal pixels and the auto-focus pixel array in the first unit pattern form a first arrangement, the normal pixels and the auto-focus pixel array in the second unit pattern form a second arrangement, and the first arrangement and the second arrangement are symmetric with respect to the first axis of symmetry.
    Type: Application
    Filed: August 18, 2021
    Publication date: October 6, 2022
    Inventors: Cheng-Hsuan LIN, Zong-Ru TU, Yu-Chi CHANG, Han-Lin WU, Hung-Jen TSAI
  • Publication number: 20220319993
    Abstract: A method of manufacturing a semiconductor device includes forming a first dielectric layer over a substrate, forming a metal layer in the first dielectric layer, forming an etch stop layer on a surface of the first dielectric layer and the metal layer, removing portions of the metal layer and the etch stop layer to form a recess in the metal layer, and forming a tungsten plug in the recess. The recess is spaced apart from a bottom surface of the etch stop layer.
    Type: Application
    Filed: March 31, 2021
    Publication date: October 6, 2022
    Inventors: Chih-Hsuan LIN, Hsi Chung CHEN, Ji-Ling WU, Chih-Teng LIAO
  • Patent number: 11463282
    Abstract: A method for sounding-interval adaptation using link quality for use in an apparatus is provided. The apparatus includes a sounding transceiver. The method includes the following steps: periodically transmitting a sounding packet to a beamformee through a downlink channel from the apparatus to the beamformee using a first sounding interval; in response to the sound transceiver successfully receiving a report packet from the beamformee to respond to the sounding packet, obtaining a current first channel profile from the report packet, and calculating a first LQ (link quality) value of the beamformee using the current first channel profile and a previous first channel profile; searching an LQ-mapping table using the first LQ value to obtain a second sounding interval; and adaptively adjusting the first sounding interval using the second sounding interval in response to a comparison result of the current first channel profile and the previous first channel profile.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: October 4, 2022
    Assignee: MEDIATEK INC.
    Inventors: Hao-Chih Yu, Pu-Hsuan Lin, Yu-Ting Su
  • Patent number: 11453743
    Abstract: A thermoset epoxy resin, its preparing composition and making process are disclosed. In particular, the thermoset epoxy resin is glycidyl ether of diphenolic bis-carbamate and formed by curing a one component epoxy composition and has a general structure as shown in formula (1).
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: September 27, 2022
    Assignee: CHANDA CHEMICAL CORP.
    Inventors: Chien-Hsin Wu, Ying-Chi Huang, Kuan-Ting Chen, Chia-Hsuan Lin, Sheng-Hong A. Dai, Ru-Jong Jeng
  • Publication number: 20220304190
    Abstract: An electronic apparatus with a cooling system includes a chassis having a mounting slot; a heat exchanger disposed in the chassis; a removable device is disposed in the mounting slot, and includes a housing and a first pump disposed in the housing; a tube is connected to the heat exchanger and the first pump and a sliding mechanism is disposed in the chassis, and connected to the tube. When the removable device is moved to a mounting location, the tube drives the sliding mechanism to a storage location. When the removable device is moved to a detachable location, the tube drives the sliding mechanism to an extension location, wherein the extension location is closer to the mounting slot than the storage location.
    Type: Application
    Filed: March 18, 2021
    Publication date: September 22, 2022
    Inventor: CHIH-HSUAN LIN