Patents by Inventor Hsuan Lin

Hsuan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220293474
    Abstract: A semiconductor device with multiple silicide regions is provided. In embodiments a first silicide precursor and a second silicide precursor are deposited on a source/drain region. A first silicide with a first phase is formed, and the second silicide precursor is insoluble within the first phase of the first silicide. The first phase of the first silicide is modified to a second phase of the first silicide, and the second silicide precursor being soluble within the second phase of the first silicide. A second silicide is formed with the second silicide precursor and the second phase of the first silicide.
    Type: Application
    Filed: May 27, 2022
    Publication date: September 15, 2022
    Inventors: Wei-Yip Loh, Yan-Ming Tsai, Hung-Hsu Chen, Chih-Wei Chang, Sheng-Hsuan Lin
  • Publication number: 20220283627
    Abstract: A portable computing device including a central processing unit (CPU) and a controller is provided. The controller is coupled between the CPU, a graphics processing unit, and a battery module. The controller determines whether to adjust performance of the CPU and the graphics processing unit according to at least one of a battery capacity, a battery power, a battery current, a battery voltage, or a battery temperature of the battery module.
    Type: Application
    Filed: February 10, 2022
    Publication date: September 8, 2022
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Hao-Hsuan Lin, Yu-Hsiu Su, Chun-Nan Wang, Jia-Ying Wu, Chia-Sen Chang, Yu-Cheng Shen, Shih-Hsiang Kao
  • Publication number: 20220285932
    Abstract: A protection circuit including a detection circuit, a current discharge element, a first transistor, and a second transistor is provided. The detection circuit is coupled between a first pad and a second pad to detect ESD events. In response to an ESD event, the detection circuit sets the detection signal to a predetermined level. The current discharge element is coupled between the first and second pads. In response to the detection signal being at the predetermined level, the current discharge element is turned on so that the ESD current passes through the current discharge element. The first transistor is coupled between a core circuit and the second pad. The second transistor is coupled between the first transistor and the second pad. In response to the detection signal being at the predetermined level, the second transistor is turned on to turn off the first transistor.
    Type: Application
    Filed: March 8, 2021
    Publication date: September 8, 2022
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chih-Hsuan LIN, Shao-Chang HUANG, Yeh-Ning JOU, Hwa-Chyi CHIOU, Ching-Ho LI
  • Publication number: 20220278199
    Abstract: A device includes a fin extending from a semiconductor substrate, a gate stack over and along a sidewall of the fin, an isolation region surrounding the gate stack, an epitaxial source/drain region in the fin and adjacent the gate stack, and a source/drain contact extending through the isolation region, including a first silicide region in the epitaxial source/drain region, the first silicide region including NiSi2, a second silicide region on the first silicide region, the second silicide region including TiSix, and a conductive material on the second silicide region.
    Type: Application
    Filed: May 16, 2022
    Publication date: September 1, 2022
    Inventors: Yan-Ming Tsai, Chih-Wei Chang, Ming-Hsing Tsai, Sheng-Hsuan Lin, Hung-Hsu Chen, Wei-Yip Loh
  • Publication number: 20220277997
    Abstract: A method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer.
    Type: Application
    Filed: May 23, 2022
    Publication date: September 1, 2022
    Inventors: Ching-Yi Chen, Sheng-Hsuan Lin, Wei-Yip Loh, Hung-Hsu Chen, Chih-Wei Chang
  • Patent number: 11426073
    Abstract: Repetitive electrical activity produces microstructural alteration in myelinated axons. These transient microstructural changes can be non-invasively visualized via two different magnetic-resonance-based approaches: diffusion fMRI and dynamic T2 spectroscopy in the ex vivo perfused bullfrog sciatic nerves. Non-invasive diffusion fMRI, based on standard diffusion tensor imaging (DTI), clearly localized the sites of axonal conduction blockage as might be encountered in neurotrauma or other lesion types. Diffusion fMRI response was graded in proportion to the total number of electrical impulses carried through a given locus. Diffusion basis spectrum imaging (DBSI) method revealed a reversible shift of tissue water into a restricted isotropic diffusion signal component, consistent with sub-myelinic vacuole formation.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: August 30, 2022
    Assignee: Washington University
    Inventors: Sheng-Kwei Song, William M. Spees, Tsen-Hsuan Lin, Peng Sun, Chunyu Song
  • Patent number: 11425483
    Abstract: A wireless charging headphone (10) includes a headphone housing (1), a speaker module (2) and a ring-shaped wireless charging module (3). The headphone housing (1) includes a front housing (11) and a cavity (s), and the front housing (11) includes a plurality of acoustic holes (111). The speaker module (2) is received inside the cavity (s) and arranged corresponding to the plurality of acoustic holes (111). The ring-shaped wireless charging module (3) is received inside the cavity (s), and the ring-shaped wireless charging module (3) is arranged between the front housing (11) and the speaker module (2). Accordingly, the wireless charging headphone (10) is able to achieve the effects of excellent design, facilitated assembly and operation stability.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: August 23, 2022
    Assignee: DEXIN CORPORATION
    Inventors: Ho-Lung Lu, Hsiu-Hsuan Lin
  • Patent number: 11411094
    Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Wen Cheng, Cheng-Tung Lin, Chih-Wei Chang, Hong-Mao Lee, Ming-Hsing Tsai, Sheng-Hsuan Lin, Wei-Jung Lin, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Wei-Yip Loh, Ya-Yi Cheng
  • Publication number: 20220246218
    Abstract: A flash memory cell includes a rectifying device and a transistor. The rectifying device has an input end coupled to a bit line. The transistor has a charge storage structure. The transistor has a first end coupled to an output end of the rectifying device, the transistor has a second end coupled to a source line, and a control end of the transistor is coupled to a word line.
    Type: Application
    Filed: February 3, 2021
    Publication date: August 4, 2022
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Feng-Min Lee, Po-Hao Tseng, Yu-Hsuan Lin, Ming-Hsiu Lee
  • Publication number: 20220246657
    Abstract: The solid-state image sensor includes a semiconductor substrate having first and second photoelectric conversion elements, a color filter layer, and a hybrid layer. The isolation structure is disposed between the first and second photoelectric conversion elements. The color filter layer is disposed above the semiconductor substrate. The hybrid layer is disposed between the semiconductor substrate and the color filter layer. The hybrid layer includes a first partition structure, a second partition structure, and a transparent layer. The first partition structure is disposed to correspond to the isolation structure. The second partition structure is surrounded by the first partition structure. The transparent layer is between the first partition structure and the second partition structure. The refractive index of the first partition structure and the refractive index of the second partition structure are lower than the refractive index of the transparent layer.
    Type: Application
    Filed: February 1, 2021
    Publication date: August 4, 2022
    Inventors: Cheng-Hsuan LIN, Yu-Chi CHANG, Zong-Ru TU
  • Publication number: 20220236951
    Abstract: A multiplication and addition operation device and a control method thereof are provided. The multiplication and addition operation device includes a feature information filter and an in-memory calculator. The feature information filter records a plurality of designated bits of a plurality of feature information, compares received input information with the designated bits to generate a comparison result, and generates a selected address according to the comparison result. The in-memory calculator records all bits of the feature information, and generates an operation result by performing a multiplication and addition operation on the feature information and the input information according to the selected address.
    Type: Application
    Filed: June 10, 2021
    Publication date: July 28, 2022
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Po-Hao Tseng, Feng-Min Lee, Yu-Hsuan Lin
  • Publication number: 20220238522
    Abstract: A method includes forming a source/drain region for a transistor, forming a first inter-layer dielectric over the source/drain region, and forming a lower source/drain contact plug over and electrically coupling to the source/drain region. The lower source/drain contact plug extends into the first inter-layer dielectric. The method further includes depositing an etch stop layer over the first inter-layer dielectric and the lower source/drain contact plug, depositing a second inter-layer dielectric over the etch stop layer, and performing an etching process to etch the second inter-layer dielectric, the etch stop layer, and an upper portion of the first inter-layer dielectric to form an opening, with a top surface and a sidewall of the lower source/drain contact plug being exposed to the opening, and forming an upper source/drain contact plug in the opening.
    Type: Application
    Filed: May 27, 2021
    Publication date: July 28, 2022
    Inventors: Ying-Yu Lai, Chih-Hsuan Lin, Hsi Chung Chen, Chih-Teng Liao
  • Publication number: 20220238151
    Abstract: An in-memory computation device and computation method are provided. The in-memory computation device, including a memory cell array, an input buffer, and a sense amplifier, is provided. The memory cell array includes a memory cell block. The memory cell block corresponds to at least one word line, and stores multiple weight values. Memory cells on the memory cell block respectively store multiple bits of each weight value. The input buffer is coupled to multiple bit lines, and respectively transmits multiple input signals to the bit lines. The memory cell array performs a multiply-add operation on the input signals and the weight values to generate multiple first operation results corresponding to multiple bit orders. The sense amplifier adds the first operation results to generate a second operation result according to the bit orders corresponding to the first operation results.
    Type: Application
    Filed: June 10, 2021
    Publication date: July 28, 2022
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Yu-Hsuan Lin, Po-Hao Tseng, Feng-Min Lee, Ming-Hsiu Lee
  • Patent number: 11387649
    Abstract: An operating circuit is provided. A first N-type transistor determines whether to create an open circuit between a core circuit and a ground terminal according to the voltage level of a specific node. An electrostatic discharge (ESD) protection circuit is coupled between an input/output pad and the core circuit to prevent an ESD current from passing through the core circuit. The ESD protection circuit includes a detection circuit and a releasing element. The detection circuit determines whether there is an ESD event at the input/output pad and generates a first detection signal according to the detection of the ESD event at the input/output pad. The releasing element provides a release path according to the first detection signal to release the ESD current. A control circuit controls the voltage level of the specific node according to the first detection signal.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: July 12, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang Huang, Li-Fan Chen, Ching-Ho Li, Ting-You Lin, Chun-Chih Chen, Kai-Chieh Hsu, Chih-Hsuan Lin, Yu-Kai Wang
  • Publication number: 20220197471
    Abstract: An electronic device with fingerprint sensing function including a fingerprint sensing array, multiple fingerprint sensing signal readout lines, multiple touch driving lines, a touch driving circuit, and a read circuit is provided. The fingerprint sensing array includes multiple fingerprint sensing units arranged in array. The fingerprint sensing signal readout lines are respectively coupled to a column of fingerprint sensing units of the fingerprint sensing array. The touch driving lines are respectively interleaved with the fingerprint sensing signal readout lines. The touch driving circuit is coupled to the touch driving lines, and provides multiple touch driving signals to the touch driving lines. The read circuit is coupled to the fingerprint sensing signal readout lines. In response to the touch driving lines outputting the touch driving signals, the read circuit determines a touch position of a touch object based on multiple read signals output by the fingerprint sensing signal readout lines.
    Type: Application
    Filed: March 11, 2020
    Publication date: June 23, 2022
    Applicant: Egis Technology Inc.
    Inventors: Chung-Yi Wang, Yu-Hsuan Lin
  • Patent number: 11366491
    Abstract: A head-mounted display device includes a body, two extension members and an adjustable fixing member. The body is adapted to lean against a front portion of a head of the user. The two extension members are disposed opposite each other. First ends of the two extension members are respectively coupled to two opposite ends of the body and configured to rotate with respect to the body so as to lean against two side portions of the head. The adjustable fixing member is coupled to each second end of the two extension members to lean against the back portion or top portion of the head, wherein the body is fixed on the head through the two extension members and the adjustable fixing member. Each of the extension members is adapted to contact or to depart from the two side portions of the head by rotating with respect to the body.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: June 21, 2022
    Assignee: HTC Corporation
    Inventors: Chih-Kai Hu, I-Hsuan Lin
  • Publication number: 20220190106
    Abstract: A semiconductor device includes at least one transistor, a shallow well region, a guard ring, and a plurality of first and second doped regions. The transistor is on a substrate and includes a source structure, a gate structure, and a drain structure. The shallow well region surrounds the transistor. The shallow well region has a first conductivity type. The guard ring surrounds the shallow well region. The guard ring has the first conductivity type. The first and second doped regions are disposed on the guard ring and surround the well region. The first doped regions and the second doped regions are alternately arranged in a shape of a loop. Each of the first doped regions and each of the second doped regions have opposite conductivity types.
    Type: Application
    Filed: December 14, 2020
    Publication date: June 16, 2022
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Karuna NIDHI, Chih-Hsuan LIN, Jian-Hsing LEE, Hwa-Chyi CHIOU
  • Publication number: 20220181370
    Abstract: An image sensor includes: a group of autofocus sensor units; neighboring sensor units adjacent to and surrounding the group of autofocus sensor units, wherein each of the neighboring sensor units has a first side close to the group of autofocus sensor units, and a second side away from the group of autofocus sensor units. The image sensor further includes: a first light shielding structure disposed between the group of autofocus sensor units and the neighboring sensor units; a first extra light shielding structure laterally extending from the first light shielding structure and disposed on at least one of the first side and the second side of one or more of the neighboring sensor units.
    Type: Application
    Filed: December 9, 2020
    Publication date: June 9, 2022
    Inventors: Cheng-Hsuan LIN, Yu-Chi CHANG
  • Patent number: 11354929
    Abstract: A fingerprint recognition device includes a light source, a light conversion layer, a light detector, and a light filter. The light source is configured to emit a first light having a first wavelength. The light conversion layer is configured to convert the first light to a second light having a second wavelength different from the first wavelength. The light detector is configured to detect the second light reflected by a fingerprint. The light filter is disposed between the light conversion layer and the light detector, and configured to substantially filter out the first light and substantially pass the second light.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: June 7, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ping-Chen Chen, Cheng-Hsuan Lin, Yu-Ling Hsu, Ding-Zheng Lin
  • Publication number: 20220169792
    Abstract: The present disclosure provides a low-dissipation flexible copper clad laminate, which includes a copper foil and a polyimide film. The polyimide film is attached to the copper foil. The polyimide film includes a polyimide, and the polyimide has a structure represented by formula (I). Formula (I) is defined as in the specification.
    Type: Application
    Filed: November 24, 2021
    Publication date: June 2, 2022
    Inventors: Ching-Hsuan LIN, Wan-Ling HSIAO