Patents by Inventor Hsueh-Chang Sung
Hsueh-Chang Sung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9117905Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming a plurality of fins, the fins being isolated from each other by an isolation structure, forming a gate structure over a portion of each fin; forming spacers on sidewalls of the gate structure, respectively, etching a remaining portion of each fin thereby forming a recess, epitaxially growing silicon to fill the recess including incorporating an impurity element selected from the group consisting of germanium (Ge), indium (In), and carbon (C), and doping the silicon epi with an n-type dopant.Type: GrantFiled: December 22, 2009Date of Patent: August 25, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Chang Su, Hsien-Hsin Lin, Tsz-Mei Kwok, Kuan-Yu Chen, Hsueh-Chang Sung, Yi-Fang Pai
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Publication number: 20150236157Abstract: A transistor device includes a gate structure disposed over a channel region of a semiconductor substrate. A source/drain recess is arranged in the semiconductor substrate alongside the gate structure. A doped silicon-germanium (SiGe) region is disposed within the source/drain recess and has a doping type which is opposite to that of the channel. An un-doped SiGe region is also disposed within the source/drain recess. The un-doped SiGe region underlies the doped SiGe region and comprises different germanium concentrations at different locations within the source/drain recess.Type: ApplicationFiled: February 14, 2014Publication date: August 20, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsz-Mei Kwok, Hsueh-Chang Sung, Kun-Mu Li, Chii-Horng Li, Tze-Liang Lee
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Publication number: 20150228724Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is overlying the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A metal silicide region is over and in contact with the second silicon germanium region.Type: ApplicationFiled: April 20, 2015Publication date: August 13, 2015Inventors: Tsz-Mei Kwok, Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee
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Publication number: 20150179796Abstract: The present disclosure relates to a transistor device having a strained source/drain region comprising a strained inducing material having a discontinuous germanium concentration profile. In some embodiments, the transistor device has a gate structure disposed onto a semiconductor substrate. A source/drain region having a strain inducing material is disposed along a side of the gate structure within a source/drain recess in the semiconductor substrate. The strain inducing material has a discontinuous germanium concentration profile along a line extending from a bottom surface of the source/drain recess to a top surface of the source/drain recess. The discontinuous germanium concentration profile provides improved strain boosting and dislocation propagation.Type: ApplicationFiled: December 19, 2013Publication date: June 25, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsueh-Chang Sung, Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li
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Publication number: 20150137183Abstract: An integrated circuit structure includes a fin field-effect transistor (FinFET) including a semiconductor fin over and adjacent to insulation regions; and a source/drain region over the insulation regions. The source/drain region includes a first and a second semiconductor region. The first semiconductor region includes silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region. The first semiconductor region has an up-slant facet and a down-slant facet. The second semiconductor region includes silicon and the element. The element has a second atomic percentage lower than the first atomic percentage. The second semiconductor region has a first portion on the up-slant facet and has a first thickness. A second portion of the second semiconductor region, if any, on the down-slant facet has a second thickness smaller than the first thickness.Type: ApplicationFiled: January 29, 2015Publication date: May 21, 2015Inventors: Tsz-Mei Kwok, Chien-Chang Su, Kuan-Yu Chen, Hsueh-Chang Sung, Hsien-Hsin Lin
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Patent number: 9012964Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is overlying the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A metal silicide region is over and in contact with the second silicon germanium region.Type: GrantFiled: August 9, 2013Date of Patent: April 21, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsz-Mei Kwok, Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee
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Patent number: 8975144Abstract: An integrated circuit structure includes a fin field-effect transistor (FinFET) including a semiconductor fin over and adjacent to insulation regions; and a source/drain region over the insulation regions. The source/drain region includes a first and a second semiconductor region. The first semiconductor region includes silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region. The first semiconductor region has an up-slant facet and a down-slant facet. The second semiconductor region includes silicon and the element. The element has a second atomic percentage lower than the first atomic percentage. The second semiconductor region has a first portion on the up-slant facet and has a first thickness. A second portion of the second semiconductor region, if any, on the down-slant facet has a second thickness smaller than the first thickness.Type: GrantFiled: November 30, 2012Date of Patent: March 10, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsz-Mei Kwok, Chien-Chang Su, Kuan-Yu Chen, Hsueh-Chang Sung, Hsien-Hsin Lin
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Publication number: 20150061024Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion.Type: ApplicationFiled: September 3, 2013Publication date: March 5, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kun-Mu Li, Tsz-Mei Kwok, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee
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Publication number: 20150048417Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A third silicon germanium region is over the second silicon germanium region, wherein the third silicon germanium region has a third germanium percentage lower than the second germanium percentage.Type: ApplicationFiled: August 16, 2013Publication date: February 19, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsz-Mei Kwok, Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee
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Publication number: 20150041852Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is overlying the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A metal silicide region is over and in contact with the second silicon germanium region.Type: ApplicationFiled: August 9, 2013Publication date: February 12, 2015Applicant: Taiwan Semiconductor Manufacturing Comapny, Ltd.Inventors: Tsz-Mei Kwok, Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee
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Publication number: 20150021696Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.Type: ApplicationFiled: July 17, 2013Publication date: January 22, 2015Inventors: Hsueh-Chang Sung, Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li
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Publication number: 20150021688Abstract: An integrated circuit structure include a semiconductor substrate, a gate stack over the semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A silicon germanium region is disposed in the opening, wherein the silicon germanium region has a first p-type impurity concentration. A silicon cap substantially free from germanium is overlying the silicon germanium region. The silicon cap has a second p-type impurity concentration greater than the first p-type impurity concentration.Type: ApplicationFiled: July 16, 2013Publication date: January 22, 2015Inventors: Hsueh-Chang Sung, Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li
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Publication number: 20140319581Abstract: A method for forming a high performance strained source-drain structure includes forming a gate structure on a substrate and forming a pocket implant region proximate to the gate structure. Spacers are formed adjacent to the gate structure. A dry etch forms a recess with a first contour; a wet etch enlarge the recess to a second contour; and a thermal etch enlarges the recess to a third contour. The source-drain structure is then formed in the recess having the third contour.Type: ApplicationFiled: April 25, 2014Publication date: October 30, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsueh-Chang Sung, Ming-Huan Tsai, Hsien-Hsin Lin, Chun-Fai Cheng, Wei-Han Fan
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Publication number: 20140308790Abstract: In a method, a gate structure is formed over a substrate, and source/drain (S/D) features are formed in the substrate and interposed by the gate structure. At least one of the S/D features is formed by forming a first semiconductor material including physically discontinuous portions, forming a second semiconductor material over the first semiconductor material, and forming a third semiconductor material over the second semiconductor material. The second semiconductor material has a composition different from a composition of the first semiconductor material. The third semiconductor material has a composition different from the composition of the second semiconductor material.Type: ApplicationFiled: June 26, 2014Publication date: October 16, 2014Inventors: Tsz-Mei KWOK, Hsueh-Chang SUNG, Kuan-Yu CHEN, Hsien-Hsin LIN
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Patent number: 8846461Abstract: A composite semiconductor structure and method of forming the same are provided. The composite semiconductor structure includes a first silicon-containing compound layer comprising an element selected from the group consisting essentially of germanium and carbon; a silicon layer on the first silicon-containing compound layer, wherein the silicon layer comprises substantially pure silicon; and a second silicon-containing compound layer comprising the element on the silicon layer. The first and the second silicon-containing compound layers have substantially lower silicon concentrations than the silicon layer. The composite semiconductor structure may be formed as source/drain regions of metal-oxide-semiconductor (MOS) devices.Type: GrantFiled: December 28, 2012Date of Patent: September 30, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Hsin Lin, Weng Chang, Chien-Chang Su, Kuan-Yu Chen, Hsueh-Chang Sung, Ming-Hua Yu
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Patent number: 8835982Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides a processing for forming improved lightly doped source/drain features and source/drain features in the semiconductor device. Semiconductor device with the improved lightly doped source/drain features and source/drain features may prevent or reduce defects and achieve high strain effect. In at least one embodiment, the lightly doped source/drain features and source/drain features comprises the same semiconductor material formed by epitaxial growth.Type: GrantFiled: February 14, 2011Date of Patent: September 16, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsz-Mei Kwok, Hsueh-Chang Sung, Kuan-Yu Chen, Hsien-Hsin Lin
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Patent number: 8815713Abstract: A method includes forming a gate stack over a semiconductor substrate, forming an opening in the semiconductor substrate and adjacent to the gate stack, and performing a first epitaxy to grow a first semiconductor layer in the first opening. An etch-back is performed to reduce a thickness of the first semiconductor layer. A second epitaxy is performed to grow a second semiconductor layer over the first semiconductor layer. The first and the second semiconductor layers have different compositions.Type: GrantFiled: November 7, 2012Date of Patent: August 26, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsueh-Chang Sung, Tsz-Mei Kwok, Kuan-Yu Chen, Kun-Mu Li
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Patent number: 8796788Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides a processing for forming improved source/drain features in the semiconductor device. Semiconductor devices with the improved source/drain features may prevent or reduce defects and achieve high strain effect resulting from epi layers. In an embodiment, the source/drain features comprises a second portion surrounding a first portion, and a third portion between the second portion and the semiconductor substrate, wherein the second portion has a composition different from the first and third portions.Type: GrantFiled: January 19, 2011Date of Patent: August 5, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsz-Mei Kwok, Hsueh-Chang Sung, Kuan-Yu Chen, Hsien-Hsin Lin
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Publication number: 20140209978Abstract: A device includes a substrate, a gate structure over the substrate, and source/drain (S/D) features in the substrate and interposed by the gate structure. At least one of the S/D features includes a first semiconductor material, a second semiconductor material over the first semiconductor material, and a third semiconductor material over the second semiconductor material. The second semiconductor material has a composition different from the first semiconductor material and the third semiconductor material. The first semiconductor material includes physically discontinuous portions.Type: ApplicationFiled: April 17, 2014Publication date: July 31, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsz-Mei KWOK, Hsueh-Chang SUNG, Kuan-Yu CHEN, Hsien-Hsin LIN
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Patent number: 8765556Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, a gate structure disposed on a portion of the substrate, and strained structures disposed at either side of the portion of the substrate and formed of a semiconductor material different from the semiconductor substrate. The portion of the substrate is T shaped having a horizontal region and a vertical region that extends from the horizontal region in a direction away from a surface of the substrate.Type: GrantFiled: December 23, 2009Date of Patent: July 1, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Rung Hsu, Chen-Hua Yu, Chao-Cheng Chen, Ming-Huan Tsai, Hsien-Hsin Lin, Hsueh-Chang Sung