Patents by Inventor Hsueh-Chang Sung
Hsueh-Chang Sung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8709897Abstract: A method for forming a high performance strained source-drain structure includes forming a gate structure on a substrate and forming a pocket implant region proximate to the gate structure. Spacers are formed adjacent to the gate structure. A dry etch forms a recess with a first contour; a wet etch enlarge the recess to a second contour; and a thermal etch enlarges the recess to a third contour. The source-drain structure is then formed in the recess having the third contour.Type: GrantFiled: November 30, 2010Date of Patent: April 29, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsueh-Chang Sung, Ming-Huan Tsai, Hsien-Hsin Lin, Chun-Fai Cheng, Wei-Han Fan
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Patent number: 8680625Abstract: An exemplary semiconductor device is described, which includes a semiconductor substrate having an active region and an isolation region. The active region has a first edge which interfaces with the isolation region. A gate structure formed on the semiconductor substrate. A spacer element abuts the gate structure and overlies the first edge. In an embodiment, the isolation region is an STI structure. An epitaxy region may be formed adjacent the spacer. In embodiments, this epitaxy region is facet-free.Type: GrantFiled: October 15, 2010Date of Patent: March 25, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Han Fan, Yu-Hsien Lin, Yimin Huang, Ming-Huan Tsai, Hsueh-Chang Sung, Chun-Fai Cheng
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Publication number: 20130299876Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, forming a material layer over the substrate and the gate structure, implanting Ge, C, P, F, or B in the material layer, removing portions of the material layer overlying the substrate at either side of the gate structure, forming recesses in the substrate at either side of the gate structure, and depositing a semiconductor material in the recesses by an expitaxy process.Type: ApplicationFiled: July 15, 2013Publication date: November 14, 2013Inventors: Kuan-Yu Chen, Hsien-Hsin Lin, Chun-Feng Nieh, Hsueh-Chang Sung, Chien-Chang Su, Tsz-Mei Kwok
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Patent number: 8558289Abstract: A transistor includes a gate electrode disposed over a substrate. At least one composite strain structure is disposed adjacent to a channel below the gate electrode. The at least one composite strain structure includes a first strain region within the substrate. A second strain region is disposed over the first strain region. At least a portion of the second strain region is disposed within the substrate.Type: GrantFiled: June 7, 2010Date of Patent: October 15, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Fai Cheng, Hsueh-Chang Sung, Kuan-Yu Chen, Hsien-Hsin Lin, Fung Ka Hing
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Patent number: 8487354Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, forming a material layer over the substrate and the gate structure, implanting Ge, C, P, F, or B in the material layer, removing portions of the material layer overlying the substrate at either side of the gate structure, forming recesses in the substrate at either side of the gate structure, and depositing a semiconductor material in the recesses by an expitaxy process.Type: GrantFiled: August 21, 2009Date of Patent: July 16, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Yu Chen, Hsien-Hsin Lin, Chun-Feng Nieh, Hsueh-Chang Sung, Chien-Chang Su, Tsz-Mei Kwok
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Patent number: 8368147Abstract: A semiconductor device having a strained channel and a method of manufacture thereof is provided. The semiconductor device has a gate electrode formed over a channel recess. A first recess and a second recess formed on opposing sides of the gate electrode are filled with a stress-inducing material. The stress-inducing material extends into an area wherein source/drain extensions overlap an edge of the gate electrode. In an embodiment, sidewalls of the channel recess and/or the first and second recesses may be along {111} facet planes.Type: GrantFiled: April 16, 2010Date of Patent: February 5, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Fai Cheng, Ka-Hing Fung, Han-Ting Tsai, Ming-Huan Tsai, Wei-Han Fan, Hsueh-Chang Sung, Haiting Wang, Wei-Yuan Lu, Hsien-Ching Lo, Kuan-Chung Chen
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Patent number: 8362575Abstract: An integrated circuit structure includes a fin field-effect transistor (FinFET) including a semiconductor fin over and adjacent to insulation regions; and a source/drain region over the insulation regions. The source/drain region includes a first and a second semiconductor region. The first semiconductor region includes silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region. The first semiconductor region has an up-slant facet and a down-slant facet. The second semiconductor region includes silicon and the element. The element has a second atomic percentage lower than the first atomic percentage. The second semiconductor region has a first portion on the up-slant facet and has a first thickness. A second portion of the second semiconductor region, if any, on the down-slant facet has a second thickness smaller than the first thickness.Type: GrantFiled: July 7, 2010Date of Patent: January 29, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsz-Mei Kwok, Chien-Chang Su, Kuan-Yu Chen, Hsueh-Chang Sung, Hsien-Hsin Lin
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Publication number: 20130001705Abstract: A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.Type: ApplicationFiled: September 10, 2012Publication date: January 3, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Chang Su, Tsz-Mei Kwok, Hsien-Hsin Lin, Hsueh-Chang Sung, Yi-Fang Pai, Kuan-Yu Chen
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Patent number: 8343872Abstract: The present disclosure provides a method of fabricating that includes providing a semiconductor substrate; forming a gate structure on the substrate; performing an implantation process to form a doped region in the substrate; forming spacers on sidewalls of the gate structure; performing an first etching to form a recess in the substrate, where the first etching removes a portion of the doped region; performing a second etching to expand the recess in the substrate, where the second etching includes an etchant and a catalyst that enhances an etching rate at a remaining portion of the doped region; and filling the recess with a semiconductor material.Type: GrantFiled: November 6, 2009Date of Patent: January 1, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsueh-Chang Sung, Hsien-Hsin Lin, Kuan-Yu Chen, Chien-Chang Su, Tsz-Mei Kwok, Yi-Fang Pai
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Patent number: 8344447Abstract: A composite semiconductor structure and method of forming the same are provided. The composite semiconductor structure includes a first silicon-containing compound layer comprising an element selected from the group consisting essentially of germanium and carbon; a silicon layer on the first silicon-containing compound layer, wherein the silicon layer comprises substantially pure silicon; and a second silicon-containing compound layer comprising the element on the silicon layer. The first and the second silicon-containing compound layers have substantially lower silicon concentrations than the silicon layer. The composite semiconductor structure may be formed as source/drain regions of metal-oxide-semiconductor (MOS) devices.Type: GrantFiled: April 5, 2007Date of Patent: January 1, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Hsin Lin, Weng Chang, Chien-Chang Su, Kuan-Yu Chen, Hsueh-Chang Sung, Ming-Hua Yu
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Patent number: 8263451Abstract: A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.Type: GrantFiled: February 26, 2010Date of Patent: September 11, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Chang Su, Tsz-Mei Kwok, Hsien-Hsin Lin, Hsueh-Chang Sung, Yi-Fang Pai, Kuan-Yu Chen
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Publication number: 20120205715Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides a processing for forming improved lightly doped source/drain features and source/drain features in the semiconductor device. Semiconductor device with the improved lightly doped source/drain features and source/drain features may prevent or reduce defects and achieve high strain effect. In at least one embodiment, the lightly doped source/drain features and source/drain features comprises the same semiconductor material formed by epitaxial growth.Type: ApplicationFiled: February 14, 2011Publication date: August 16, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsz-Mei KWOK, Hsueh-Chang SUNG, Kuan-Yu CHEN, Hsien-Hsin LIN
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Publication number: 20120181625Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides a processing for forming improved source/drain features in the semiconductor device. Semiconductor devices with the improved source/drain features may prevent or reduce defects and achieve high strain effect resulting from epi layers. In an embodiment, the source/drain features comprises a second portion surrounding a first portion, and a third portion between the second portion and the semiconductor substrate, wherein the second portion has a composition different from the first and third portions.Type: ApplicationFiled: January 19, 2011Publication date: July 19, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsz-Mei KWOK, Hsueh-Chang SUNG, Kuan-Yu CHEN, Hsien-Hsin LIN
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Publication number: 20120132957Abstract: A method for forming a high performance strained source-drain structure includes forming a gate structure on a substrate and forming a pocket implant region proximate to the gate structure. Spacers are formed adjacent to the gate structure. A dry etch forms a recess with a first contour; a wet etch enlarge the recess to a second contour; and a thermal etch enlarges the recess to a third contour. The source-drain structure is then formed in the recess having the third contour.Type: ApplicationFiled: November 30, 2010Publication date: May 31, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsueh-Chang Sung, Ming-Huan Tsai, Hsien-Hsin Lin, Chun-Fai Cheng, Wei-Han Fan
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Publication number: 20120091539Abstract: An exemplary semiconductor device is described, which includes a semiconductor substrate having an active region and an isolation region. The active region has a first edge which interfaces with the isolation region. A gate structure formed on the semiconductor substrate. A spacer element abuts the gate structure and overlies the first edge. In an embodiment, the isolation region is an STI structure. An epitaxy region may be formed adjacent the spacer. In embodiments, this epitaxy region is facet-free.Type: ApplicationFiled: October 15, 2010Publication date: April 19, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Han Fan, Yu-Hsien Lin, Yimin Huang, Ming-Huan Tsai, Hsueh-Chang Sung, Chun-Fai Cheng
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Publication number: 20110254105Abstract: A semiconductor device having a strained channel and a method of manufacture thereof is provided. The semiconductor device has a gate electrode formed over a channel recess. A first recess and a second recess formed on opposing sides of the gate electrode are filled with a stress-inducing material. The stress-inducing material extends into an area wherein source/drain extensions overlap an edge of the gate electrode. In an embodiment, sidewalls of the channel recess and/or the first and second recesses may be along {111} facet planes.Type: ApplicationFiled: April 16, 2010Publication date: October 20, 2011Applicant: Taiwan Semiconductor Manufacturing Company. Ltd.Inventors: Chun-Fai Cheng, Ka-Hing Fung, Han-Ting Tsai, Ming-Huan Tsai, Wei-Han Fan, Hsueh-Chang Sung, Haiting Wang, Wei-Yuan Lu, Hsien-Ching Lo, Kuan-Chung Chen
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Publication number: 20110210404Abstract: A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.Type: ApplicationFiled: February 26, 2010Publication date: September 1, 2011Applicant: Taiwan Seminconductor Manufacturing Company, Ltd.Inventors: Chien-Chang Su, Tsz-Mei Kwok, Hsien-Hsin Lin, Hsueh-Chang Sung, Yi-Fang Pai, Kuan-Yu Chen
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Publication number: 20110147846Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming a plurality of fins, the fins being isolated from each other by an isolation structure, forming a gate structure over a portion of each fin; forming spacers on sidewalls of the gate structure, respectively, etching a remaining portion of each fin thereby forming a recess, epitaxially growing silicon to fill the recess including incorporating an impurity element selected from the group consisting of germanium (Ge), indium (In), and carbon (C), and doping the silicon epi with an n-type dopant.Type: ApplicationFiled: December 22, 2009Publication date: June 23, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTDInventors: Chien-Chang Su, Hsien-Hsin Lin, Tsz-Mei Kwok, Kuan-Yu Chen, Hsueh-Chang Sung, Yi-Fang Pai
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Publication number: 20110108894Abstract: The present disclosure provides a method of fabricating that includes providing a semiconductor substrate; forming a gate structure on the substrate; performing an implantation process to form a doped region in the substrate; forming spacers on sidewalls of the gate structure; performing an first etching to form a recess in the substrate, where the first etching removes a portion of the doped region; performing a second etching to expand the recess in the substrate, where the second etching includes an etchant and a catalyst that enhances an etching rate at a remaining portion of the doped region; and filling the recess with a semiconductor material.Type: ApplicationFiled: November 6, 2009Publication date: May 12, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsueh-Chang Sung, Hsien-Hsin Lin, Kuan-Yu Chen, Chien-Chang Su, Tsz-Mei Kwok, Yi-Fang Pai
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Publication number: 20110073952Abstract: An integrated circuit structure includes a fin field-effect transistor (FinFET) including a semiconductor fin over and adjacent to insulation regions; and a source/drain region over the insulation regions. The source/drain region includes a first and a second semiconductor region. The first semiconductor region includes silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region. The first semiconductor region has an up-slant facet and a down-slant facet. The second semiconductor region includes silicon and the element. The element has a second atomic percentage lower than the first atomic percentage. The second semiconductor region has a first portion on the up-slant facet and has a first thickness. A second portion of the second semiconductor region, if any, on the down-slant facet has a second thickness smaller than the first thickness.Type: ApplicationFiled: July 7, 2010Publication date: March 31, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsz-Mei Kwok, Chien-Chang Su, Kuan-Yu Chen, Hsueh-Chang Sung, Hsien-Hsin Lin