Patents by Inventor Hsun Wang

Hsun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9871101
    Abstract: A semiconductor structure, and methods for forming the semiconductor device are provided. In various embodiments, the semiconductor device includes a substrate, source/drain regions over the substrate, a plurality of nanowires over the substrate and sandwiched by the source/drain regions, a gate dielectric layer surrounding the plurality of nanowires, and a gate layer surrounding the gate dielectric layer.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: January 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Gerben Doornbos, Chun-Hsiung Lin, Chien-Hsun Wang, Carlos H. Diaz
  • Publication number: 20180012674
    Abstract: A heat keeping structure includes an additive, a first powdered substance and a second powdered substance. The additive and the first powdered substance are mixed to form the second powdered substance which is molded by a spinning device to form the heat keeping structure. The additive includes a radioactive mineral substance, a calcium silicate substance and a halobios calcium which are mixed and treated by a nanotechnology. Thus, the heat keeping structure has radioactive and activating functions, promotes blood circulation and has a heat keeping effect by provision of the radioactive mineral substance. In addition, the heat keeping structure has low thermal conductivity and has a heat storage function by provision of the calcium silicate substance. Further, the heat keeping structure has antibacterial, mildewproof, moisture absorption, deodorizing and anti-static effects by provision of the halobios calcium.
    Type: Application
    Filed: July 7, 2016
    Publication date: January 11, 2018
    Inventor: Yeh-Hsun Wang
  • Publication number: 20180012807
    Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.
    Type: Application
    Filed: September 1, 2017
    Publication date: January 11, 2018
    Inventors: I-Wen WU, Hsien-Cheng Wang, Mei-Yun Wang, Shih-Wen Liu, Chao-Hsun Wang, Yun Lee
  • Patent number: 9865460
    Abstract: A method for forming a semiconductor device having a fin-type channel is provided. The method may include the following operations: forming a first buffer layer over a substrate; forming a first dielectric layer over the first buffer layer; patterning the first dielectric layer over the first buffer layer; forming a barrier layer over the first buffer layer; forming a second dielectric layer over the barrier layer; patterning the second dielectric layer over the barrier layer; forming a channel layer over the barrier layer; and patterning the second dielectric layer, such that at least a portion of the channel layer protrudes to form the fin-type channel.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: January 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chien-Hsun Wang, Chun-Hsiung Lin, Mao-Lin Huang
  • Patent number: 9853102
    Abstract: A tunnel field-effect transistor and method fabricating the same are provided. The tunnel field-effect transistor includes a drain region, a source region with opposite conductive type to the drain region, a channel region disposed between the drain region and the source region, a metal gate layer disposed around the channel region, and a high-k dielectric layer disposed between the metal gate layer and the channel region.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: December 26, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Teng-Chun Tsai, Li-Ting Wang, Cheng-Tung Lin, De-Fang Chen, Chih-Tang Peng, Chien-Hsun Wang, Hung-Ta Lin
  • Publication number: 20170351167
    Abstract: An illumination system of a projection system includes a first illumination integrating element, a second illumination integrating element, first light source elements, and second light source elements. The first/second illumination integrating element includes first/second light-reflecting regions separated from each other and located on a first/second plane. The second plane is not parallel to the first plane. The first/second light source elements are adapted to provide first/second light beams respectively. The first/second light-reflecting regions are located on a transmission path of the first/second light beams, and the first/second light beams are adapted to travel along the illumination direction after being reflected by the first/second light-reflecting regions. The illumination system has good optical quality. The projection system has good image quality.
    Type: Application
    Filed: May 31, 2017
    Publication date: December 7, 2017
    Inventors: Hsuan-I Wu, Chi-Hsun Wang, Hao-Wei Chiu, Ko-Shun Chen
  • Patent number: 9810968
    Abstract: A wavelength conversion device including a main body and a transparent element is provided. The main body has at least one wavelength conversion region, a containing recess portion, and a stop portion. The containing recess portion and the stop portion encircle a closed slot. The transparent element is disposed in the closed slot to construct a light penetration region. The stop portion stops the transparent element along a radial direction of the main body. Moreover, a projector using the wavelength conversion device is also mentioned.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: November 7, 2017
    Assignee: Coretronic Corporation
    Inventors: Kun-Liang Jao, Ko-Shun Chen, Chi-Hsun Wang, Chi-Tang Hsieh
  • Publication number: 20170315430
    Abstract: An illumination system and a projection device are disclosed. The illumination system includes laser light sources, a color wheel element and light combiners. The laser light sources provide laser lights of different colors. One of the laser light sources is disposed on an optical axis. The color wheel element is disposed on the optical axis and on a transmission path of the laser lights, and adjusts wavelengths of the laser lights. The light combiners are disposed on the optical axis and between the laser light source and the color wheel element. The light combiners are pervious to the laser lights or reflect the laser lights to combine the laser lights on the optical axis. The illumination system uses the laser light sources to provide lights of different colors, and in collaboration with a configuration structure of the optical elements thereof, the laser lights with a wider color gamut are provided.
    Type: Application
    Filed: April 18, 2017
    Publication date: November 2, 2017
    Applicant: Coretronic Corporation
    Inventors: Chi-Hsun Wang, Chang-Hsuan Chen, Hsuan-I Wu, Ko-Shun Chen
  • Publication number: 20170312294
    Abstract: The present invention relates to synergistic combinations of lupeol acetate and curcumin at low dosage, and their use for the treatment or prevention of osteoporosis.
    Type: Application
    Filed: July 14, 2017
    Publication date: November 2, 2017
    Inventors: Jeng-Jong HWANG, Wei-Hsun WANG
  • Publication number: 20170293212
    Abstract: An illumination system including at least one light source, a reflection cover, a wavelength conversion element, and a filter element is provided. A focal point of the reflection cover is disposed on an extension line of a transmission path of an excitation beam provided by the light source, and an opening of the reflection cover is adjacent to the focal point. The wavelength conversion element penetrates through the opening, and has a light-action region. The light-action region is disposed on the transmission path of the excitation beam, and converts the excitation beam into a conversion beam. The reflection cover is disposed on a transmission path of the conversion beam. The filter element is disposed on a transmission path of the conversion beam from the reflection cover. The conversion beam from the reflection cover is obliquely incident to the filter element, and the filter element filters the conversion beam.
    Type: Application
    Filed: April 7, 2017
    Publication date: October 12, 2017
    Applicant: Coretronic Corporation
    Inventors: Chi-Hsun Wang, Chang-Hsuan Chen, Hsuan-I Wu, Ko-Shun Chen
  • Patent number: 9786757
    Abstract: This disclosure provides a horizontal structure by using a double STI recess method. The double STI recess method includes: forming a plurality of fins on the substrate; forming shallow trench isolation between the fins; performing first etch-back on the shallow trench isolation; forming source and drain regions adjacent to channels of the fins; and performing second etch-back on the shallow trench isolations to expose a lower portion of the fins as a larger process window for forming gates of the fins.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: October 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Huan-Chieh Su, Jui-Chien Huang, Chun-An Lin, Chien-Hsun Wang, Chun-Hsiung Lin
  • Patent number: 9779984
    Abstract: A method of fabricating a semiconductor device includes forming a first dielectric layer over a substrate that includes a gate structure, forming a first trench in the first dielectric layer, forming dielectric spacers along sidewalls of the first trench, removing a portion of the dielectric spacers to expose a portion of the sidewalls, forming a first metal feature in the first trench over the another portion of the dielectric spacers and along the exposed portions of the sidewalls of the first trench, forming a second dielectric layer over the first metal feature and the gate structure and forming a second trench through the second dielectric layer to expose a portion of the first metal feature and a third trench through the second dielectric layer and the first dielectric layer to expose a portion of the gate structure in the same etching process.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: October 3, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hsun Wang, Hsien-Cheng Wang, Mei-Yun Wang
  • Publication number: 20170278751
    Abstract: Self-aligned contacts are provided. In an embodiment the self-aligned contacts are formed by partially removing a first dielectric material from adjacent to a gate electrode and fully removing a second dielectric material from adjacent to the gate electrode. A conductive material is deposited into the regions of the removed first dielectric material and the second dielectric material, and the conductive material and metal gates are recessed below a spacer. A dielectric layer is deposited over the recessed conductive material and the recessed metal gates, and the self-aligned contacts are formed through the dielectric layer.
    Type: Application
    Filed: June 12, 2017
    Publication date: September 28, 2017
    Inventors: Chao-Hsun Wang, Shih-Wen Liu, Fu-Kai Yang, Hsien-Cheng Wang, Mei-Yun Wang
  • Publication number: 20170278744
    Abstract: A method of fabricating a semiconductor device includes forming a first dielectric layer over a substrate that includes a gate structure, forming a first trench in the first dielectric layer, forming dielectric spacers along sidewalls of the first trench, removing a portion of the dielectric spacers to expose a portion of the sidewalls, forming a first metal feature in the first trench over the another portion of the dielectric spacers and along the exposed portions of the sidewalls of the first trench, forming a second dielectric layer over the first metal feature and the gate structure and forming a second trench through the second dielectric layer to expose a portion of the first metal feature and a third trench through the second dielectric layer and the first dielectric layer to expose a portion of the gate structure in the same etching process.
    Type: Application
    Filed: June 9, 2016
    Publication date: September 28, 2017
    Inventors: Chao-Hsun Wang, Hsien-Cheng Wang, Mei-Yun Wang
  • Patent number: 9773868
    Abstract: Transistor devices and methods for forming transistor devices are provided. A transistor device includes a semiconductor substrate and a device layer. The device layer includes a source region and a drain region connected by a suspended nanowire channel. First and second etch stop layers are respectively arranged beneath the source region and the drain region. Each of the etch stop layers forms a support structure interposed between the semiconductor substrate and the respective source and drain regions.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: September 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsun Wang, Mao-Lin Huang, Chun-Hsiung Lin, Jean-Pierre Colinge
  • Patent number: 9765026
    Abstract: The present invention provides novel crystalline forms of apremilast hemitoluene solvate, apremilast hydrate, and apremilast anhydrate and an amorphous form of apremilast, and processes for the preparation of these forms.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: September 19, 2017
    Assignee: SCINOPHARM TAIWAN, LTD.
    Inventors: Hsiao-ping Fang, Wei-Shuo Lo, Kuan Hsun Wang, Yu-Sheng Lin, Tsung-Cheng Hu, YuanChang Huang
  • Patent number: 9765079
    Abstract: Crystalline forms of pemetrexed diacid are provided (Forms 1 and 2) which are readily produced for either laboratory-scale or industrial scale. Processes for the preparation of Forms 1 and 2 are also provided.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: September 19, 2017
    Assignee: SCINTOPHARM TAIWAN, LTD.
    Inventors: Ying-Tzu Lin, Kuan-Hsun Wang, Wei-Shuo Lo, Wen-Wei Lin, Wan-Yin Cheng
  • Publication number: 20170263749
    Abstract: An embodiment of a method for forming a transistor that includes providing a semiconductor substrate having a source/drain region is provided where a first SiGe layer is formed over the source/drain region. A thermal oxidation is performed to convert a top portion of the first SiGe layer to an oxide layer and a bottom portion of the first SiGe layer to a second SiGe layer. A thermal diffusion process is performed after the thermal oxidation is performed to form a SiGe area from the second SiGe layer. The SiGe area has a higher Ge concentration than the first SiGe layer.
    Type: Application
    Filed: May 19, 2017
    Publication date: September 14, 2017
    Inventors: Chih-Hao Chang, Jeff J. XU, Chien-Hsun WANG, Chih Chieh YEH, Chih-Hsiang CHANG
  • Publication number: 20170260186
    Abstract: A process for preparing an amorphous form of idelalisib comprises: (a) forming a first solution of idelalisib in a solvent; (b) adding the first solution obtained in step (a) into water to form a second solution; (c) optionally cooling the second solution obtained in step (b) and; (d) isolating the optionally cooled second solution from step (c) to provide the amorphous form of idelalisib. Mild reaction conditions are used in this process. The amorphous form of idelalisib prepared by this process is stable and does not transfer to other crystalline forms easily. This process is suitable for large scale manufacture of idelalisib at a high yield.
    Type: Application
    Filed: March 1, 2017
    Publication date: September 14, 2017
    Inventors: Tsung-Cheng Hu, Wei-Shuo Lo, Kuan-Hsun Wang, Wan-Yin Cheng
  • Publication number: 20170253597
    Abstract: Crystalline forms of pemetrexed diacid are provided (Forms 1 and 2) which are readily produced for either laboratory-scale or industrial scale. Processes for the preparation of Forms 1 and 2 are also provided.
    Type: Application
    Filed: May 10, 2016
    Publication date: September 7, 2017
    Inventors: Ying-Tzu Lin, Kuan-Hsun Wang, Wei-Shuo Lo, Wen-Wei Lin, Wan-Yin Cheng