Abstract: According to an exemplary embodiment, a method of forming a vertical structure with at least two barrier layers is provided. The method includes the following operations: providing a substrate; providing a vertical structure over the substrate; providing a first barrier layer over a source, a channel, and a drain of the vertical structure; and providing a second barrier layer over a gate and the drain of the vertical structure.

Abstract: A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.

Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate and a gate dielectric layer formed over the fin structure. The FinFET device structure includes a gate electrode layer formed over the gate dielectric later and a gate contact structure formed over the gate electrode layer. The gate contact structure includes a first conductive layer formed over the gate electrode layer, a barrier layer formed over the first conductive layer and a second conductive layer over the barrier layer. The second conductive layer is electrically connected to the gate electrode layer by the first conductive layer.

Abstract: An ultrasonic biometric sensor comprises a detection chip. The detection chip includes a substrate, an ultrasonic transducer array and a control circuit. The ultrasonic transducer array is arranged on the substrate, including a plurality of arrayed piezoelectric elements. Each piezoelectric element is disposed on a floating membrane. The floating membrane is suspended in the opening side of a cavity by at least one support arm extending transversely. The control circuit is also arranged on the substrate and electrically connected with each piezoelectric element through the support arm to control the ultrasonic transducer array to generate an ultrasonic signal and read the reflected ultrasonic signal received by the ultrasonic transducer array. The ultrasonic biometric sensor is easy to fabricate and has a high yield.

Abstract: A conductive layer is formed between a metal gate structure, which includes a high-k gate dielectric layer and a gate electrode, and a contact feature. The conductive layer can be selectively deposited on a top surface of the gate electrode or, alternatively, non-selectively formed on the top surface of the gate electrode and the gate dielectric layer by controlling, for example, time of deposition. The conductive layer can have a bottom portion embedded into the gate electrode. The conductive layer and the contact feature can include the same composition, though they may be formed using different deposition techniques.

Abstract: A FinFET device structure is provided. The FinFET device structure includes a gate structure formed over a fin structure and an S/D contact structure formed over the fin structure. The FinFET device structure also includes an S/D conductive plug formed over the S/D contact structure, and the S/D conductive plug includes a first barrier layer and a first conductive layer. The FinFET device structure includes a gate contact structure formed over the gate structure, and the gate contact structure includes a second barrier layer and a second conductive layer. The FinFET device structure includes a first isolation layer surrounding the S/D conductive plug, and the first barrier layer is between the first isolation layer and the first conductive layer. A second isolation layer surrounding the gate contact structure, and the second barrier layer is between the second isolation layer and the second conductive layer.

Abstract: A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.

Abstract: A light source module including a blue laser light source, an adjusting light source, a wavelength conversion device, and a light combiner is provided. The wavelength conversion device is disposed on an optical path of a first blue beam provided by the blue laser light source and an optical path of an adjusting beam provided by the adjusting light source. When a first transmissive area of the wavelength conversion device is cut into the optical path of the first blue beam, the blue laser light source and the adjusting light source are simultaneously turned on. A transmission direction of the first blue beam passing through the first transmissive area is opposite to a transmission direction of the adjusting beam passing through the first transmissive area. The light combiner combines the first blue beam and the adjusting beam into a second blue beam. Moreover, a projection apparatus is provided.

Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.

Abstract: A method includes forming a transistor including forming a source/drain region on a side of a dummy gate stack, forming a first Inter-Layer Dielectric (ILD) covering the source/drain region, and replacing the dummy gate stack with a replacement gate stack. The method further includes forming a second ILD over the first ILD and the replacement gate stack, and forming a lower source/drain contact plug electrically coupling to the source/drain region. The lower source/drain contact plug penetrates through both the first ILD and the second ILD. A third ILD is formed over the second ILD. A gate contact plug is formed in the second ILD and the third ILD. An upper source/drain contact plug is formed overlapping and contacting the lower source/drain contact plug. The upper source/drain contact plug penetrates through the third ILD. The upper source/drain contact plug and the gate contact plug are formed of different materials.

Abstract: A method includes forming a transistor including forming a source/drain region on a side of a dummy gate stack, forming a first Inter-Layer Dielectric (ILD) covering the source/drain region, and replacing the dummy gate stack with a replacement gate stack. The method further includes forming a second ILD over the first ILD and the replacement gate stack, and forming a lower source/drain contact plug electrically coupling to the source/drain region. The lower source/drain contact plug penetrates through both the first ILD and the second ILD. A third ILD is formed over the second ILD. A gate contact plug is formed in the second ILD and the third ILD. An upper source/drain contact plug is formed overlapping and contacting the lower source/drain contact plug. The upper source/drain contact plug penetrates through the third ILD. The upper source/drain contact plug and the gate contact plug are formed of different materials.

Abstract: An illumination system includes a plurality of light source modules and at least one condenser lens. Each of the light source modules includes a first color light source and a wavelength conversion element. The first color light source is configured to provide a first color beam as an excitation beam. The wavelength conversion element is disposed on a transmission path of the first color beam and configured to convert the first color beam into a converted beam. The at least one condenser lens is disposed on transmission paths of the plurality of converted beams from the plurality of wavelength conversion elements and the plurality of first color beams. A projection apparatus including the illumination system is also provided.

Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.

Abstract: A method for forming a self-aligned contact is provided. In an embodiment, a metal gate is formed on a substrate, and a gate spacer is formed adjacent the metal gate. A conductive plug is formed over the substrate, with the gate spacer disposed between the metal gate and the conductive plug. The metal gate and the conductive plug are recessed. A first dielectric layer is deposited over the gate spacer, over the metal gate, over the conductive plug, and along sidewalls of the metal gate. A first opening is formed in the first dielectric layer exposing the metal gate, and a second opening is formed in the first dielectric layer exposing the conductive plug. The first opening and the second opening are filled with a first conductive material.

Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.

Abstract: In a method of manufacturing a semiconductor device, a support layer is formed over a substrate. A patterned semiconductor layer made of a first semiconductor material is formed over the support layer. A part of the support layer under a part of the semiconductor layer is removed, thereby forming a semiconductor wire. A semiconductor shell layer made of a second semiconductor material different from the first semiconductor material is formed around the semiconductor wire.

Abstract: A zirconia nanoparticle material includes a zirconia nanoparticle and a carbonate coordinated on a surface of the zirconia nanoparticle. The carbonate is 1 to 10 parts by weight of the zirconia nanoparticle.

Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.

Abstract: A method includes forming a transistor including forming a source/drain region on a side of a dummy gate stack, forming a first Inter-Layer Dielectric (ILD) covering the source/drain region, and replacing the dummy gate stack with a replacement gate stack. The method further includes forming a second ILD over the first ILD and the replacement gate stack, and forming a lower source/drain contact plug electrically coupling to the source/drain region. The lower source/drain contact plug penetrates through both the first ILD and the second ILD. A third ILD is formed over the second ILD. A gate contact plug is formed in the second ILD and the third ILD. An upper source/drain contact plug is formed overlapping and contacting the lower source/drain contact plug. The upper source/drain contact plug penetrates through the third ILD. The upper source/drain contact plug and the gate contact plug are formed of different materials.