Patents by Inventor Hsun Wang

Hsun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11189525
    Abstract: Various embodiments of the present disclosure provide a via-first process for connecting a contact to a gate electrode. In some embodiments, the contact is formed extending through a first interlayer dielectric (ILD) layer to a source/drain region bordering the gate electrode. An etch stop layer (ESL) is deposited covering the first ILD layer and the contact, and a second ILD layer is deposited covering the ESL. A first etch is performed into the first and second ILD layers and the etch stop layer to form a first opening exposing the gate electrode. A series of etches is performed into the second ILD layer and the etch stop layer to form a second opening overlying the contact and overlapping the first opening, such that a bottom of the second opening slants downward from the contact to the first opening. A gate-to-contact (GC) structure is formed filling the first and second openings.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: November 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Hsun Wang, Mei-Yun Wang, Kuo-Yi Chao, Wang-Jung Hsueh
  • Publication number: 20210364359
    Abstract: An infrared temperature sensor comprises a thermopile sensing chip. The thermopile sensing chip includes a chip substrate, a thermopile sensing unit, a heater and a temperature sensing element. The thermopile sensing unit is disposed on the chip substrate, receives infrared thermal radiation from a target and outputs a corresponding infrared sensation signal. The heater is disposed on the chip substrate and used to heat the chip substrate to a working temperature. The temperature sensing element is disposed on the chip substrate, senses the working temperature of the chip substrate and outputs a corresponding working temperature signal. In operation, the infrared temperature sensor can maintain the thermopile sensing unit at the preset working temperature. Thereby, a single-point temperature calibration is sufficient to obtain more accurate measurement results in a broad environmental temperature range.
    Type: Application
    Filed: July 9, 2020
    Publication date: November 25, 2021
    Inventors: Chein-Hsun WANG, Chen-Tang HUANG, Yu-Chih LIANG, Jenping KU
  • Publication number: 20210367043
    Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.
    Type: Application
    Filed: August 3, 2021
    Publication date: November 25, 2021
    Inventors: Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Chen-Yuan Kao
  • Patent number: 11177212
    Abstract: A method and structure for forming semiconductor device includes forming a contact via opening in a first dielectric layer, where the contact via opening exposes a first portion of a contact etch stop layer (CESL). The method further includes etching both the first portion of the CESL exposed by the contact via opening and adjacent lateral portions of the CESL to expose a source/drain contact and form an enlarged contact via opening having cavities disposed on either side of a bottom portion of the enlarged contact via opening. The method further includes forming a passivation layer on sidewall surfaces of the enlarged contact via opening including on sidewall surfaces of the cavities. The method further includes depositing a first metal layer within the enlarged contact via opening and within the cavities to provide a contact via in contact with the exposed source/drain contact.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang
  • Publication number: 20210331287
    Abstract: A grinding and polishing simulation method, a grinding and polishing simulation system and a grinding and polishing process transferring method. The grinding and polishing simulation method includes the following steps. A sensing information of a grinding and polishing apparatus when grinding or polishing a workpiece is obtained. A plurality of model parameters is identified according to the sensing information. At least one quality parameter is calculated according to a machining path, a plurality of process parameters and the plurality of model parameters.
    Type: Application
    Filed: December 28, 2020
    Publication date: October 28, 2021
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yuan-Chieh LO, Yu-Hsun WANG, Pei-Chun LIN, Chih-Hsuan SHIH, Shu HUANG
  • Patent number: 11158727
    Abstract: The present disclosure provides a method of semiconductor fabrication that includes forming a semiconductor fin protruding from a substrate, the semiconductor fin including a plurality of first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked, the second semiconductor material being different from the first semiconductor material in composition; forming a first gate stack on the semiconductor fin; forming a recess in the semiconductor fin within a source/drain (S/D) region adjacent to the first gate stack, a sidewall of the first and second semiconductor material layers being exposed within the recess; performing an etching process to the semiconductor fin, resulting in an undercut below the first gate stack; epitaxially growing on the sidewall of the semiconductor fin to fill in the undercut with a semiconductor extended feature of the first semiconductor material; and growing an epitaxial S/D feature from the rece
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: October 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pei-Hsun Wang, Chih-Chao Chou, Chun-Hsiung Lin, Ching-Wei Tsai, Chih-Hao Wang
  • Publication number: 20210327768
    Abstract: A method includes forming an epitaxy semiconductor layer over a semiconductor substrate, and etching the epitaxy semiconductor layer and the semiconductor substrate to form a semiconductor strip, which includes an upper portion acting as a mandrel, and a lower portion under the mandrel. The upper portion is a remaining portion of the epitaxy semiconductor layer, and the lower portion is a remaining portion of the semiconductor substrate. The method further includes growing a first semiconductor fin starting from a first sidewall of the mandrel, growing a second semiconductor fin starting from a second sidewall of the mandrel. The first sidewall and the second sidewall are opposite sidewalls of the mandrel. A first transistor is formed based on the first semiconductor fin. A second transistor is formed based on the second semiconductor fin.
    Type: Application
    Filed: June 28, 2021
    Publication date: October 21, 2021
    Inventors: Pei-Hsun Wang, Shih-Cheng Chen, Chun-Hsiung Lin, Chih-Hao Wang
  • Publication number: 20210320061
    Abstract: A method and structure for forming semiconductor device includes forming a contact via opening in a first dielectric layer, where the contact via opening exposes a first portion of a contact etch stop layer (CESL). The method further includes etching both the first portion of the CESL exposed by the contact via opening and adjacent lateral portions of the CESL to expose a source/drain contact and form an enlarged contact via opening having cavities disposed on either side of a bottom portion of the enlarged contact via opening. The method further includes forming a passivation layer on sidewall surfaces of the enlarged contact via opening including on sidewall surfaces of the cavities. The method further includes depositing a first metal layer within the enlarged contact via opening and within the cavities to provide a contact via in contact with the exposed source/drain contact.
    Type: Application
    Filed: April 13, 2020
    Publication date: October 14, 2021
    Inventors: Po-Yu HUANG, Shih-Che LIN, Chao-Hsun WANG, Kuo-Yi CHAO, Mei-Yun WANG
  • Publication number: 20210313448
    Abstract: The present disclosure provides a method of semiconductor fabrication. The method includes forming a fin protruding from a substrate, the fin having a first sidewall and a second sidewall opposing the first sidewall; forming a sacrificial dielectric layer on the first and second sidewalls and a top surface of the fin; etching the sacrificial dielectric layer to remove the sacrificial dielectric layer from the second sidewall of the fin; forming a recess in the fin; growing an epitaxial source/drain (S/D) feature from the recess, the epitaxial S/D feature having a first sidewall and a second sidewall opposing the first sidewall, wherein the sacrificial dielectric layer covers the first sidewall of the epitaxial S/D feature; recessing the sacrificial dielectric layer, thereby exposing the first sidewall of the epitaxial S/D feature; and forming an S/D contact on the first sidewall of the epitaxial S/D feature.
    Type: Application
    Filed: April 1, 2020
    Publication date: October 7, 2021
    Inventors: Pei-Hsun Wang, Kuo-Cheng Chiang, Chih-Hao Wang
  • Patent number: 11139379
    Abstract: A semiconductor structure is provided. The semiconductor structure includes nanostructures over a substrate, a gate stack around the nanostructures, a gate spacer layer alongside the gate stack, an inner spacer layer between the gate spacer layer and the nanostructures, a source/drain feature adjoining the nanostructures, a contact plug over the source/drain feature, and a silicon germanium layer along the surface of the source/drain feature and between the contact plug and the inner spacer layer.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: October 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhi-Chang Lin, Shih-Cheng Chen, Kuo-Cheng Chiang, Pei-Hsun Wang, Chih-Hao Wang
  • Publication number: 20210296985
    Abstract: The power supply controller is for use in a power supply circuit, for reducing acoustic noise. The power supply control circuit generates a control signal according to a voltage identification (VID) signal and a voltage sense signal, to operate a power switch in a power stage circuit, thus converting an input voltage to an output voltage. The power supply control circuit includes a conversion circuit and a PWM control circuit. The conversion circuit includes a DAC and a slope control circuit. When the power supply controller operates in an acoustic noise reduction mode and when a present level is higher than a requested level, the slope control circuit adjusts a descending slope of an analog voltage identification signal which is generated according to the VID signal, so as to restrain a decrease velocity of the output voltage to be higher than zero but not higher than a predetermined velocity.
    Type: Application
    Filed: January 11, 2021
    Publication date: September 23, 2021
    Inventors: Chia-Chi Liu, Yu-Chieh Lin, Yen-Hsun Wang, Ruei-Pei Jiang
  • Patent number: 11127684
    Abstract: A contact structure of a semiconductor device includes a gate contact in contact with a gate structure and extending through a first dielectric layer, a source/drain contact in contact with a source/drain feature and extending through the first dielectric layer, a common rail line in contact with the gate contact and the source/drain contact, and a power rail line in contact with the common rail line and electrically coupled to a ground of the semiconductor device.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: September 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hsun Wang, Wang-Jung Hsueh, Kuo-Yi Chao, Mei-Yun Wang, Ru-Gun Liu
  • Patent number: 11121037
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack and a second gate stack over a substrate. The substrate has a base, a first fin structure, and a second fin structure over the base, the second fin structure is wider than the first fin structure. The method includes partially removing the first fin structure, which is not covered by the first gate stack, and the second fin structure, which is not covered by the second gate stack. The method includes forming an inner spacer layer over the first fin structure, which is not covered by the first gate stack. The method includes forming a first stressor and a second stressor respectively over the inner spacer layer and the second fin structure, which is not covered by the second gate stack.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: September 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ching-Wei Tsai, Yu-Xuan Huang, Kuan-Lun Cheng, Chih-Hao Wang, Min Cao, Jung-Hung Chang, Lo-Heng Chang, Pei-Hsun Wang, Kuo-Cheng Chiang
  • Publication number: 20210273104
    Abstract: A semiconductor device according to the present disclosure includes a first isolation feature and a second isolation feature, a fin structure extending lengthwise along a first direction and sandwiched between the first isolation feature and the second isolation feature along a second direction perpendicular to the first direction, a first channel member disposed over the first isolation feature, a second channel member disposed over the second isolation feature, and a gate structure disposed over and wrapping around the first channel member and the second channel member.
    Type: Application
    Filed: December 23, 2020
    Publication date: September 2, 2021
    Inventors: Pei-Hsun Wang, Chun-Hsiung Lin, Cheng-Ting Chung, Chih-Hao Wang
  • Patent number: 11107896
    Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Chen-Yuan Kao
  • Publication number: 20210265483
    Abstract: A semiconductor device includes a semiconductor substrate having a fin structure, a gate stack across the fin structure, a spacer structure on a sidewall of the gate stack, an epitaxial structure on the semiconductor substrate, and a dielectric structure in the spacer structure. The dielectric structure extends along a lower portion of the spacer structure and across the fin structure.
    Type: Application
    Filed: February 24, 2020
    Publication date: August 26, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Hsun Wang, Shih-Cheng Chen, Kuo-Cheng Chiang, Chih-Hao Wang
  • Publication number: 20210265202
    Abstract: Various embodiments of the present disclosure provide a via-first process for connecting a contact to a gate electrode. In some embodiments, the contact is formed extending through a first interlayer dielectric (ILD) layer to a source/drain region bordering the gate electrode. An etch stop layer (ESL) is deposited covering the first ILD layer and the contact, and a second ILD layer is deposited covering the ESL. A first etch is performed into the first and second ILD layers and the etch stop layer to form a first opening exposing the gate electrode. A series of etches is performed into the second ILD layer and the etch stop layer to form a second opening overlying the contact and overlapping the first opening, such that a bottom of the second opening slants downward from the contact to the first opening. A gate-to-contact (GC) structure is formed filling the first and second openings.
    Type: Application
    Filed: February 21, 2020
    Publication date: August 26, 2021
    Inventors: Chao-Hsun Wang, Mei-Yun Wang, Kuo-Yi Chao, Wang-Jung Hsueh
  • Publication number: 20210257248
    Abstract: A method includes forming a first conductive feature over a semiconductor substrate, forming an ILD layer over the first conductive feature, patterning the ILD layer to form a trench, and forming a conductive layer over the patterned ILD layer to fill the trench. The method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ILD layer, polishing the exposed top surface of the ILD layer, such that a top portion of the via contact protrudes from the exposed top surface of the ILD layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature.
    Type: Application
    Filed: July 31, 2020
    Publication date: August 19, 2021
    Inventors: Pang-Sheng Chang, Chao-Hsun Wang, Kuo-YI Chao, Fu-Kai Yang, Mei-Yun Wang, Li-Chieh Wu, Chun-Wei Hsu
  • Publication number: 20210249509
    Abstract: A device includes a first semiconductor strip protruding from a substrate, a second semiconductor strip protruding from the substrate, an isolation material surrounding the first semiconductor strip and the second semiconductor strip, a nanosheet structure over the first semiconductor strip, wherein the nanosheet structure is separated from the first semiconductor strip by a first gate structure including a gate electrode material, wherein the first gate structure partially surrounds the nanosheet structure, and a first semiconductor channel region and a semiconductor second channel region over the second semiconductor strip, wherein the first semiconductor channel region is separated from the second semiconductor channel region by a second gate structure including the gate electrode material, wherein the second gate structure extends on a top surface of the second semiconductor strip.
    Type: Application
    Filed: February 11, 2020
    Publication date: August 12, 2021
    Inventors: Pei-Yu Wang, Pei-Hsun Wang
  • Publication number: 20210226020
    Abstract: A semiconductor structure is provided. The semiconductor structure includes nanostructures over a substrate, a gate stack around the nanostructures, a gate spacer layer alongside the gate stack, an inner spacer layer between the gate spacer layer and the nanostructures, a source/drain feature adjoining the nanostructures, a contact plug over the source/drain feature, and a silicon germanium layer along the surface of the source/drain feature and between the contact plug and the inner spacer layer.
    Type: Application
    Filed: January 16, 2020
    Publication date: July 22, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhi-Chang LIN, Shih-Cheng CHEN, Kuo-Cheng CHIANG, Pei-Hsun WANG, Chih-Hao WANG