Abstract: A device includes a first semiconductor strip protruding from a substrate, a second semiconductor strip protruding from the substrate, an isolation material surrounding the first semiconductor strip and the second semiconductor strip, a nanosheet structure over the first semiconductor strip, wherein the nanosheet structure is separated from the first semiconductor strip by a first gate structure including a gate electrode material, wherein the first gate structure partially surrounds the nanosheet structure, and a first semiconductor channel region and a semiconductor second channel region over the second semiconductor strip, wherein the first semiconductor channel region is separated from the second semiconductor channel region by a second gate structure including the gate electrode material, wherein the second gate structure extends on a top surface of the second semiconductor strip.

Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity ?-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity ?-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity ?-W phase. The ?-W converts to a low-resistivity ?-phase of tungsten in the regions not pre-treated with impurities.

Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.

Abstract: A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.

Abstract: Provided is a method of manufacturing a semiconductor device including providing a semiconductor substrate, and forming an epitaxial stack on the semiconductor substrate. The epitaxial stack comprises a plurality of first epitaxial layers interposed by a plurality of second epitaxial layers. The method further includes patterning the epitaxial stack and the semiconductor substrate to form a semiconductor fin, recessing a portion of the semiconductor fin to form source/drain spaces; and laterally removing portions of the plurality of first epitaxial layers exposed by the source/drain spaces to form a plurality of cavities. The method further includes forming inner spacers in the plurality of cavities, performing a treatment process to remove an inner spacer residue in the source/drain spaces, forming S/D features in the source/drain spaces, and forming a gate structure engaging the semiconductor fin.

Abstract: An infant care apparatus includes a piezoelectric sensor and an infrared array sensor. The piezoelectric sensor senses a respiration rate and a heart rate of an infant. The infrared array sensor senses a body temperature and an occupancy state of the infant in a non-contact manner. The abovementioned infant care apparatus can assist in determining an abnormality of the respiration rate and the heart rate of the infant based on the occupancy state of the infant output by the infrared array sensor, so as to reduce a false alarm rate.

Abstract: An infrared temperature sensor comprises a first communication port and a second communication port. A plurality of infrared temperature sensors can be cascaded to each other and connected to an external host controller through the second communication port. The external host controller can set up and administer the unique addresses of the plurality of the infrared temperature sensors through the second communication port, whereby to selectively perform multicasting communication or unicasting communication with the plurality of infrared temperature sensors through the first communication port. The infrared temperature sensor further comprises a second thermopile sensing element used to sense the thermal radiation of a package structure, whereby to compensate for the measurement error induced by temperature variation of the package structure. Thus, the measurement accuracy is increased.

Abstract: The present disclosure provides a method of semiconductor fabrication. The method includes forming a fin protruding from a substrate, the fin having a first sidewall and a second sidewall opposing the first sidewall; forming a sacrificial dielectric layer on the first and second sidewalls and a top surface of the fin; etching the sacrificial dielectric layer to remove the sacrificial dielectric layer from the second sidewall of the fin; forming a recess in the fin; growing an epitaxial source/drain (S/D) feature from the recess, the epitaxial S/D feature having a first sidewall and a second sidewall opposing the first sidewall, wherein the sacrificial dielectric layer covers the first sidewall of the epitaxial S/D feature; recessing the sacrificial dielectric layer, thereby exposing the first sidewall of the epitaxial S/D feature; and forming an S/D contact on the first sidewall of the epitaxial S/D feature.

Abstract: Various embodiments of the present disclosure provide a via-first process for connecting a contact to a gate electrode. In some embodiments, the contact is formed extending through a first interlayer dielectric (ILD) layer to a source/drain region bordering the gate electrode. An etch stop layer (ESL) is deposited covering the first ILD layer and the contact, and a second ILD layer is deposited covering the ESL. A first etch is performed into the first and second ILD layers and the etch stop layer to form a first opening exposing the gate electrode. A series of etches is performed into the second ILD layer and the etch stop layer to form a second opening overlying the contact and overlapping the first opening, such that a bottom of the second opening slants downward from the contact to the first opening. A gate-to-contact (GC) structure is formed filling the first and second openings.

Abstract: A method for forming a FinFET device structure is provided. The method includes forming a fin structure over a substrate and forming a gate dielectric layer over the fin structure. The method also includes forming a gate electrode layer over the gate dielectric layer and forming a source/drain (S/D) structure adjacent to the gate electrode layer. In addition, the method includes forming an S/D contact structure over the S/D structure. The method also includes forming a first conductive layer in direct with the gate electrode layer. A bottom surface of the first conductive layer is lower than a top surface of the gate dielectric layer. The method further includes forming a second conductive layer over the first conductive layer. The gate electrode layer is electrically connected to the second conductive layer by the first conductive layer.

Abstract: A semiconductor structure includes a fin disposed on a substrate, the fin including a channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein. The semiconductor structure further includes a gate stack engaging the channel region of the fin and gate spacers disposed between the gate stack and the source and drain regions of the fin, wherein each channel of the channels includes a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers, wherein a concentration of germanium in the middle section of the channel is higher than a concentration of germanium in the two end sections of the channel, and wherein the middle section of the channel further includes a core portion and an outer portion surrounding the core portion with a germanium concentration profile from the core portion to the outer portion.

Abstract: In a method of manufacturing a semiconductor device, a support layer is formed over a substrate. A patterned semiconductor layer made of a first semiconductor material is formed over the support layer. A part of the support layer under a part of the semiconductor layer is removed, thereby forming a semiconductor wire. A semiconductor shell layer made of a second semiconductor material different from the first semiconductor material is formed around the semiconductor wire.

Abstract: A spliced display including a transparent substrate, a plurality of micro (light-emitting diodes) LEDs, and a plurality of light sensors is provided. The transparent substrate has a display surface and a back surface opposite to each other. The driving backplanes are disposed on the back surface of the transparent substrate to be spliced with each other. The micro LEDs are disposed on the driving backplanes respectively and located between the micro LEDs and the transparent substrate. Each of the driving backplanes is corresponding to parts of the micro LEDs. The light sensors are disposed on the transparent substrate and located between the driving backplanes and the transparent substrate. Each of the light sensors is adjacent to at least two of the micro LEDs, and at least one of the at least two of the micro LEDs is adjacent to two of the light sensor.

Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity ?-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity ?-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity ?-W phase. The ?-W converts to a low-resistivity ?-phase of tungsten in the regions not pre-treated with impurities.

Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.

Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a substrate. The substrate has a base and a multilayer structure over the base, and the gate stack wraps around the multilayer structure. The method includes partially removing the multilayer structure, which is not covered by the gate stack. The multilayer structure remaining under the gate stack forms a multilayer stack, and the multilayer stack includes a sacrificial layer and a channel layer over the sacrificial layer. The method includes partially removing the sacrificial layer to form a recess in the multilayer stack. The method includes forming an inner spacer layer in the recess and a bottom spacer over a sidewall of the channel layer. The method includes forming a source/drain structure over the bottom spacer. The bottom spacer separates the source/drain structure from the channel layer.

Abstract: A semiconductor device includes a semiconductor substrate having a fin structure, a gate stack across the fin structure, a spacer structure on a sidewall of the gate stack, an epitaxial structure on the semiconductor substrate, and a dielectric structure in the spacer structure. The dielectric structure extends along a lower portion of the spacer structure and across the fin structure.

Abstract: A semiconductor device according to the present disclosure includes first gate-all-around (GAA) devices in a first device area and second GAA devices in a second device area. Each of the first GAA devices includes a first vertical stack of channel members, a first gate structure over and around the first vertical stack of channel members, and a plurality of inner spacer features. Each of the second GAA devices includes a second vertical stack of channel members and a second gate structure over and around the second vertical stack of channel members. Two adjacent channel members of the first vertical stack of channel members are separated by a portion of the first gate structure and at least one of the plurality of inner spacer features. Two adjacent channel members of the second vertical stack of channel members are separated only by a portion of the second gate structure.

Abstract: A microfluidic device and a biological detection method using the microfluidic device are provided. The microfluidic device includes a sample mixing area, an optical indicator mixing area and an observation area. The sample mixing area stores barcode beads and configured to receive a test sample to mix the barcode beads with the test sample, in which the barcode beads correspond to different detecting targets. The optical indicator mixing area is configured to receive an optical indicator and the barcode beads to mix the barcode beads with the optical indicator. The observation area is configured to receive the barcode beads from the optical indicator mixing area. In the biological detection method, at first, images of the barcode beads are captured. Thereafter, images of reacted barcode beads are determined, and values of barcode patterns thereof are recognized to determine reacting targets of the test sample.