Patents by Inventor Hsun Wang

Hsun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10923598
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer including different semiconductor materials, and the fin comprises a channel region and a source/drain region; forming a dummy gate structure over the channel region of the fin and over the substrate; etching a portion of the fin in the source/drain region to form a trench therein, wherein a bottom surface of the trench is below a bottom surface of the second semiconductor layer; selectively removing an edge portion of the second semiconductor layer in the channel region such that the second semiconductor layer is recessed; forming a sacrificial structure around the recessed second semiconductor layer and over the bottom surface of the trench; and epitaxially growing a source/drain feature in the source/drain region of the fin.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: February 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Hsun Wang, Chun-Hsiung Lin, Chih-Hao Wang
  • Patent number: 10923573
    Abstract: A conductive layer is formed between a metal gate structure, which includes a high-k gate dielectric layer and a gate electrode, and a contact feature. The conductive layer can be selectively deposited on a top surface of the gate electrode or, alternatively, non-selectively formed on the top surface of the gate electrode and the gate dielectric layer by controlling, for example, time of deposition. The conductive layer can have a bottom portion embedded into the gate electrode. The conductive layer and the contact feature can include the same composition, though they may be formed using different deposition techniques.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: February 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hsun Wang, Yu-Feng Yin, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao
  • Publication number: 20210020524
    Abstract: A method includes forming an epitaxy semiconductor layer over a semiconductor substrate, and etching the epitaxy semiconductor layer and the semiconductor substrate to form a semiconductor strip, which includes an upper portion acting as a mandrel, and a lower portion under the mandrel. The upper portion is a remaining portion of the epitaxy semiconductor layer, and the lower portion is a remaining portion of the semiconductor substrate. The method further includes growing a first semiconductor fin starting from a first sidewall of the mandrel, growing a second semiconductor fin starting from a second sidewall of the mandrel. The first sidewall and the second sidewall are opposite sidewalls of the mandrel. A first transistor is formed based on the first semiconductor fin. A second transistor is formed based on the second semiconductor fin.
    Type: Application
    Filed: July 18, 2019
    Publication date: January 21, 2021
    Inventors: Pei-Hsun Wang, Shih-Cheng Chen, Chun-Hsiung Lin, Chih-Hao Wang
  • Publication number: 20200388504
    Abstract: A semiconductor structure includes a metal gate structure including a gate dielectric layer and a gate electrode, the gate electrode including at least a first metal; a conductive layer formed above the gate electrode, the conductive layer including an alloy layer, the alloy layer including at least the first metal and a second metal different from the first metal, the alloy layer extending from a position below a top surface of the metal gate structure to a position above the top surface of the metal gate structure; and a contact feature disposed above the metal gate structure, wherein the contact feature is in direct contact with a top surface of the conductive layer.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Inventors: Pang-Sheng Chang, Yu-Feng Yin, Chao-Hsun Wang, Kuo-Yi Chao, Fu-Kai Yang, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao, Chia-Yang Hung, Chia-Sheng Chang, Shu-Huei Suen, Jyu-Horng Shieh, Sheng-Liang Pan, Jack Kuo-Ping Kuo, Shao-Jyun Wu
  • Patent number: 10861740
    Abstract: A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hsun Wang, Hsien-Cheng Wang, Mei-Yun Wang
  • Publication number: 20200381545
    Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a first semiconductor channel member and a second semiconductor channel member extending between the first and second source/drain features, and a first dielectric feature and a second dielectric feature each including a first dielectric layer and a second dielectric layer different from the first dielectric layer. The first and second dielectric features are sandwiched between the first and second semiconductor channel members.
    Type: Application
    Filed: December 5, 2019
    Publication date: December 3, 2020
    Inventors: Kuo-Cheng Chiang, Zhi-Chang Lin, Shih-Cheng Chen, Chih-Hao Wang, Pei-Hsun Wang, Lo-Heng Chang, Jung-Hung Chang
  • Patent number: 10847426
    Abstract: Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a first gate strip and a second gate strip. The substrate has at least one first fin in a first region, at least one second fin in a second region and an isolation layer covering lower portions of the first and second fins. The first fin includes a first material layer and a second material layer over the first material layer, and the interface between the first material layer and the second material layer is uneven. The first gate strip is disposed across the first fin. The second gate strip is disposed across the second fin.
    Type: Grant
    Filed: October 28, 2018
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semicondutor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Wang, Jui-Chien Huang, Kuo-Cheng Ching, Chun-Hsiung Lin, Pei-Hsun Wang
  • Patent number: 10825919
    Abstract: A method of fabricating semiconductor devices is provided. The method includes forming a fin structure on a substrate, in which the fin structure includes a fin stack of alternating first and second semiconductor layers and forming recesses in the fin stack at source and drain regions. The method also includes etching the second semiconductor layers to form recessed second semiconductor layers, and forming third semiconductor layers on sidewalls of the recessed second semiconductor layers. The method further includes epitaxially growing source and drain structures in the recesses, removing the recessed second semiconductor layers to form spaces between the first semiconductor layers, and oxidizing the third semiconductor layers to form inner spacers. In addition, the method includes forming a gate structure to fill the spaces and to surround the first semiconductor layers.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: November 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hsiung Lin, Pei-Hsun Wang, Chih-Hao Wang, Kuo-Cheng Ching, Jui-Chien Huang
  • Publication number: 20200343140
    Abstract: Semiconductor structures and methods for forming the same are provided. The method includes forming a fin protruding from a substrate and forming an isolation structure surrounding the fin. The method also includes epitaxially growing channel fins on sidewalls of the fin over the isolation structure and etching the fin to form a space between the channel fins. The method further includes forming a gate structure to fill the space between the channel fins.
    Type: Application
    Filed: July 9, 2020
    Publication date: October 29, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Hsun WANG, Chun-Hsiung LIN, Chih-Hao WANG, Chih-Chao CHOU
  • Publication number: 20200335388
    Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.
    Type: Application
    Filed: July 6, 2020
    Publication date: October 22, 2020
    Inventors: Teng-Chun TSAI, Bing-Hung CHEN, Chien-Hsun WANG, Cheng-Tung LIN, Chih-Tang PENG, De-Fang CHEN, Huan-Just LIN, Li-Ting WANG, Yung-Cheng LU
  • Patent number: 10811515
    Abstract: Methods of fabricating semiconductor devices are provided. The method includes forming a gate structure over a substrate, forming a disposable spacer on a sidewall of the gate structure, and forming a source region and a drain region at opposite sides of the gate structure. The method also includes depositing an interlayer dielectric layer around the disposable spacer, and forming a first hard mask on the interlayer dielectric layer. The method further includes removing an upper portion of the gate structure, and removing the disposable spacer to form a trench between the gate structure and the interlayer dielectric layer. In addition, the method includes sealing the trench to form an air-gap spacer, and forming a second hard mask on the gate structure.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hsiung Lin, Pei-Hsun Wang, Chih-Chao Chou, Chia-Hao Chang, Chih-Hao Wang
  • Patent number: 10804162
    Abstract: A method that includes forming first semiconductor layers and second semiconductor layers disposed over a substrate, wherein the first and second semiconductor layers have different material compositions, are alternatingly disposed, and extend over first and second regions of the substrate; patterning the first and the second semiconductor layers to form a first fin in the first region and a second fin in the second region; removing the first semiconductor layers from the first and second fins such that a first portion of the patterned second semiconductor layers becomes first suspended nanostructures in the first fin and that a second portion of the patterned second semiconductor layers becomes second suspended nanostructures in the second fin; forming third semiconductor layers on the second suspended nanostructures in the second fin; and performing an anneal process to drive materials contained in the third semiconductor layers into corresponding second suspended nanostructures in the second fin.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hao Wang, Jui-Chien Huang, Chun-Hsiung Lin, Kuo-Cheng Chiang, Chih-Chao Chou, Pei-Hsun Wang
  • Patent number: 10790197
    Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: I-Wen Wu, Hsien-Cheng Wang, Mei-Yun Wang, Shih-Wen Liu, Chao-Hsun Wang, Yun Lee
  • Publication number: 20200273964
    Abstract: A method of fabricating semiconductor devices is provided. The method includes forming a fin structure on a substrate, in which the fin structure includes a fin stack of alternating first and second semiconductor layers and forming recesses in the fin stack at source and drain regions. The method also includes etching the second semiconductor layers to form recessed second semiconductor layers, and forming third semiconductor layers on sidewalls of the recessed second semiconductor layers. The method further includes epitaxially growing source and drain structures in the recesses, removing the recessed second semiconductor layers to form spaces between the first semiconductor layers, and oxidizing the third semiconductor layers to form inner spacers. In addition, the method includes forming a gate structure to fill the spaces and to surround the first semiconductor layers.
    Type: Application
    Filed: February 21, 2019
    Publication date: August 27, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hsiung LIN, Pei-Hsun WANG, Chih-Hao WANG, Kuo-Cheng CHING, Jui-Chien HUANG
  • Patent number: 10755945
    Abstract: A method includes forming a metal gate structure, wherein the metal gate structure includes a gate dielectric layer and a gate electrode; performing a surface treatment to a top surface of the metal gate structure, wherein the surface treatment converts a top portion of the gate electrode to an oxidation layer; forming a conductive layer above the gate electrode, wherein the forming of the conductive layer includes substituting oxygen in the oxidation layer with a metallic element; and forming a contact feature above the metal gate structure, wherein the contact feature is in direct contact with the conductive layer.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pang-Sheng Chang, Yu-Feng Yin, Chao-Hsun Wang, Kuo-Yi Chao, Fu-Kai Yang, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao, Chia-Yang Hung, Chia-Sheng Chang, Shu-Huei Suen, Jyu-Horng Shieh, Sheng-Liang Pan, Jack Kuo-Ping Kuo, Shao-Jyun Wu
  • Patent number: 10739439
    Abstract: A laser positioning system includes a laser scanner, a first positioning tag, a second positioning tag, and a processing unit. The laser scanner is disposed on a mobile carrier and is for emitting a light beam to a positioning board and receiving a plurality of reflected light spot signals generated by the light beam reflected from the positioning board. The first positioning tag and the second positioning tag are for reflecting the light beam to generate a first positioning signal and a second positioning signal to the laser scanner. The processing unit is for finding information of positions of the light beam projected on the first positioning tag and the second positioning tag, and filtering the reflected light spot signals to define a reference coordinate for the processing to calculate relative positions of the laser scanner and the positioning board according to the reference coordinate.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: August 11, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chun-Te Wu, Chieh-Chih Wang, Chung-Hsun Wang
  • Publication number: 20200249101
    Abstract: A thermal sensor package for earbuds includes two thermopile sensor elements on a single thermopile sensor chip, and the two thermopile sensor elements are separated by a block wall of a cap. One of the thermopile sensor elements senses external infrared thermal radiation through a window of the cap, and the other thermopile sensor element senses internal infrared thermal radiation from a package structure as a basis for correcting compensation. Therefore, the foregoing thermal sensor package for earbuds can quickly correct a measurement error caused by the package structure to improve the measurement accuracy. In addition, the forgoing thermal sensor package for earbuds has a simple packaging step and is easy to arrange a silicon based infrared lens to expand its application.
    Type: Application
    Filed: June 14, 2019
    Publication date: August 6, 2020
    Inventors: Chein-Hsun WANG, Ming LE, Yu-Chih LIANG, Tung Yang LEE, Chih-Yung TSAI
  • Patent number: 10732495
    Abstract: An illumination system includes a coherent light source, a first light-combining device, an optical wavelength conversion module, and a first auxiliary light source. The coherent light source emits a coherent light beam. The first light-combining device is disposed on a transmission path of the coherent light beam. The light wavelength conversion module is disposed on a transmission path of the coherent light beam transmitted from the first light-combining device and converts the coherent light beam into a first converted light beam, and reflects the first converted light beam back to the first light-combining device. The first auxiliary light source emits a first auxiliary light beam which is transmitted to the first light-combining device. The first light-combining device combines the first auxiliary light beam and the first converted light beam. A projection apparatus and a method for driving the illumination system are also provided.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: August 4, 2020
    Assignee: Coretronic Corporation
    Inventors: Chi-Tang Hsieh, Ko-Shun Chen, Chi-Hsun Wang, Hao-Wei Chiu, Hou-Sheng Wang, Chien-Chung Liao, Yin-Cheng Lin, De-Sheng Yang, Ming-Tsung Weng
  • Patent number: 10727134
    Abstract: A method of fabricating semiconductor devices is provided. The method includes forming a fin protruding from a substrate, and forming a disposable mandrel fin on the fin. The method also includes epitaxially growing channel fins on sidewalls of the disposable mandrel fin. The method further includes removing the disposable mandrel fin to form a space between the channel fins, and forming a gate structure to fill the space between the channel fins and to wrap the channel fins. In addition, the method includes forming source and drain structures on opposite sides of the gate structure.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pei-Hsun Wang, Chun-Hsiung Lin, Chih-Hao Wang, Chih-Chao Chou
  • Patent number: D906426
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: December 29, 2020
    Assignee: E Ink Holdings Inc.
    Inventor: Chi-Hsun Wang