Abstract: The present disclosure provides a semiconductor device and a method for fabricating a semiconductor buried layer. The method includes: preparing a substrate which includes a first oxide layer; forming a first buried layer region in the surface of the substrate by using a photoresist layer with a first buried layer region pattern as a mask, in which a doping state of the first buried layer region is different from a doping state of other region of the substrate; forming a second oxide layer on the surface of the substrate and the first buried layer region; and forming a second buried layer region in the surface of the substrate through self alignment process by using the second oxide layer as a mask. The method disclosed by the present disclosure reduces the complexity of the buried layer procedures and the cost thereof, as well as the probability of crystal defects.

Abstract: Cationic poly(ester amide) (PEA)-based hydrogels are provided. The hydrogels are fabricated from unsaturated L-arginine base poly(ester-amide) (UArg-PEA) precursors, pluronicDA precursors, or a combination of UArg-PEA and pluronicDA precursors at predetermined precursor composition ratios. PluronicDA/UArg-PEA hybrid hydrogels and pure pluronicDA based hydrogels are thermoresponsive and biodegradable, while pure UArg-PEA base hydrogels are biodegradable but not thermoresponsive. UArg-PEA based, pluronicDA based and hybrid hydrogels can be synthesized from unsaturated arginine-based PEA salts and/or unsaturated pluronic acid polymers. Unsaturated pluronic acid polymers can be synthesized by reacting pluronic acid with acryloylchloride to provided functional vinyl groups at the two chain ends of pluronic acid. The hydrogels can be used to carry and/or release molecules or compounds such as bioactive compounds, and can function as biologic carriers for a variety of biomedical applications.

Abstract: Mask design techniques for detection and removal of undesirable artifacts in SADP processes using multiple patterns are disclosed. Artifacts or spurs result from lithographic and chemical processing of semiconducting wafers. The spurs are undesirable because they can cause unwanted connections or act as electrical antennas. Spurs are detected using rule-based techniques and reduced by modifying lithographic masks. The severity of the detected spurs is determined, again using rule-based techniques. The effects of detected spurs can be reduced by modifying the decomposition of the drawn patterns into the two masks used for lithography. Mandrel masks are modified by add dummy mandrel material, and trim masks are modified by removing trim material. The resulting multi-pattern arrangement is used to fabricate the critical design elements that make up the semiconductor wafers.

Abstract: Mask design techniques for detection and removal of undesirable artifacts in SADP processes using multiple patterns are disclosed. Artifacts or spurs result from lithographic and chemical processing of semiconducting wafers. The spurs are undesirable because they can cause unwanted connections or act as electrical antennas. Spurs are detected using rule-based techniques and reduced by modifying lithographic masks. The severity of the detected spurs is determined, again using rule-based techniques. The effects of detected spurs can be reduced by modifying the decomposition of the drawn patterns into the two masks used for lithography. Mandrel masks are modified by add dummy mandrel material, and trim masks are modified by removing trim material. The resulting multi-pattern arrangement is used to fabricate the critical design elements that make up the semiconductor wafers.

Abstract: In one embodiment of the invention, a method of synthesizing physical gates from register transfer logic code for an integrated circuit design is disclosed. The method includes reading a register transfer level (RTL) input file describing an integrated circuit design; parsing and translating the RTL input file into a plurality of Boolean logic equations; translating the plurality of Boolean logic equations into a plurality of logic primitives; placing the plurality of logic primitives into a floorplan of the integrated circuit design, wherein the placement of the plurality of logic primitives defines wire interconnects; and optimizing each of the plurality of Boolean logic equations in response to wire costs and wire timing delays.

Abstract: Processes and apparatuses are described for modeling and correcting electron-beam (e-beam) proximity effects during e-beam lithography. An uncalibrated e-beam model, which includes a long-range component and a short-range component, can be calibrated based on one or more test layouts. During correction, a first resist intensity map can be computed based on the long-range component of the calibrated e-beam model and a mask layout. Next, a target pattern in the mask layout can be corrected by, iteratively: (1) computing a second resist intensity map based on the short-range component of the calibrated e-beam model and the target pattern; (2) obtaining a combined resist intensity map by combining the first resist intensity map and the second resist intensity map; and (3) adjusting the target pattern based on the combined resist intensity map and the design intent.

Abstract: Mask design techniques for sharp corner printing in liquid crystal displays are disclosed using multiple patterns. The viewing angle and color quality of thin film transistor liquid crystal displays are largely dependent upon electrode corner sharpness as patterned in a given metal layer. Depending on design style, critical elements include convex angles, concave angles, or both convex and concave angles. Angle sharpness is dependent upon the resolution limit of a given exposure system. Since critical design element requirements exceed the capabilities of one mask, two or more masks are implemented. The determination of critical pattern features within a given layer identifies angles that are problematic for fabrication. The critical pattern features are decomposed into multiple mask layers. The resulting multi-pattern arrangement is used to fabricate the critical design elements that make up the needed angles.

Abstract: Systems and techniques for modeling the EUV lithography shadowing effect are described. Some embodiments described herein provide a process model that includes an EUV lithography shadowing effect component. Polygon edges in a layout can be dissected into a set of segments. Next, the EUV lithography shadowing effect component can be used to bias each segment. The modified layout having the biased segments can then be used as input for other components in the process model.

Abstract: One embodiment of the present invention provides a system that accurately models polarization states of an illumination source in an optical lithography system for manufacturing integrated circuits. During operation, the system starts by receiving a two-dimensional (2D) grid map for an illumination source pupil in the optical lithography system. The system then constructs a source-polarization model for the illumination source by defining a polarization state at each grid point in the grid map. Next, the system enhances a lithography model for the optical lithography system by incorporating the source-polarization model into the lithography/OPC model.

Abstract: The present disclosure provides a semiconductor device and a method for fabricating a semiconductor buried layer. The method includes: preparing a substrate which includes a first oxide layer; forming a first buried layer region in the surface of the substrate by using a photoresist layer with a first buried layer region pattern as a mask, in which a doping state of the first buried layer region is different from a doping state of other region of the substrate; forming a second oxide layer on the surface of the substrate and the first buried layer region; and forming a second buried layer region in the surface of the substrate through self alignment process by using the second oxide layer as a mask. The method disclosed by the present disclosure reduces the complexity of the buried layer procedures and the cost thereof, as well as the probability of crystal defects.

Abstract: Extreme ultraviolet (EUV) lithography flare calculation and compensation is disclosed herein. A method of calculating flare for a mask for use in EUV lithography includes decomposing the flare power spectrum density (PSD) into a low frequency component and a high frequency component. Further, the method includes receiving a plurality of layouts in a flare map generator. Each of the plurality of layouts corresponds to a chip pattern location on the mask. Moreover, the method includes generating, using the flare map generator, a low frequency flare map for the mask from the low frequency component by using fast Fourier transform (FFT).

Abstract: One embodiment of the present invention provides a system that determines image intensity at a location in a photoresist (PR) layer on a wafer. During operation, the system receives a set of masks which were used to generate one or more patterned layers of a multilayer structure on the wafer, wherein a patterned layer includes a set of reflectors on a top surface of the patterned layer, which correspond to patterns in a patterned-layer mask in the set of masks, wherein a reflector reflects light from a light source during a photolithography process. The system then generates a first virtual mask based on the first mask and the patterned-layer mask, wherein the first virtual mask uses a clear area to model a reflector in the set of reflectors. Next, the system determines the image intensity value at the location on the PR layer based at least on the first mask and the first virtual mask.

Abstract: Display apparatuses are provided. The display apparatus includes a light source package generating light, a circuit board including a recessed region in which the light source package is disposed, a display panel displaying images, and a light guide plate directing the light generated from the light source package onto the display panel. The light guide plate includes a top surface, a bottom surface, and a plurality of sidewall surfaces. One of the sidewall surfaces of the light guide plate is a light incident surface on which the light from the light source package is irradiated. A distance between the light source package and the light incident surface is less than a width of the circuit board.

Abstract: The present disclosure introduces a method and an apparatus of shrinking virtual hard disk image file. The present techniques search a garbage data block in a file and revise a record of the garbage data block in a block allocation table (BAT). The file includes one or more data blocks and a BAT that records information of each data block. The garbage data block is a data block that does not store effective data. The present techniques move an effective data block subsequent to the garbage data block, revise a record of the effective data block in the BAT after the moving, and shrink a size of the file after the movement.

Abstract: A method for enabling a MIMO operation mode in a multimode communication terminal includes switching a first channel module to have parameter characteristics consistent with those of a second channel module, so that the multimode communication terminal enables the MIMO operation mode by using the first channel module and the second channel module at the same time. The method also includes extracting corresponding parameters from the second channel module and configuring the first channel module to be switched with the extracted parameters, such that the first channel module and second channel module enable the multimode communication terminal to perform MIMO communication. The method further includes issuing, upon determination of a switch, notification instructions to means in channel switch layer means and changing a data channel associated with the first channel module, such that the first channel module and second channel module can be adapted to the MIMO operation mode.

Abstract: Extreme ultraviolet (EUV) lithography flare calculation and compensation is disclosed herein. A method of calculating flare for a mask for use in EUV lithography includes decomposing the flare power spectrum density (PSD) into a low frequency component and a high frequency component. Further, the method includes receiving a plurality of layouts in a flare map generator. Each of the plurality of layouts corresponds to a chip pattern location on the mask. Moreover, the method includes generating, using the flare map generator, a low frequency flare map for the mask from the low frequency component by using fast Fourier transform (FFT).

Abstract: The present invention discloses a method and apparatus for detecting timing constraint conflicts, the method comprising: receiving a timing constraint file; taking all test points in the timing constraint file as nodes, determining directed edges between the nodes and weights of the directed edges according to timing constraints relevant to the test points in the timing constraint file to establish a directed graph; searching for all directed cycles of the directed graph; and for each directed cycle, if the sum of the weights of the directed edges constituting the directed cycle satisfies a required condition, determining that a timing constraint conflict exists among the test points and the timing constraints constituting the directed cycle. The method and apparatus can automatically detect timing constraint conflicts with one hundred percent to reduce design turnaround time and engineer resources in ASIC projects.

Abstract: Systems and techniques for modeling the EUV lithography shadowing effect are described. Some embodiments described herein provide a process model that includes an EUV lithography shadowing effect component. Polygon edges in a layout can be dissected into a set of segments. Next, the EUV lithography shadowing effect component can be used to bias each segment. The modified layout having the biased segments can then be used as input for other components in the process model.

Abstract: The present invention provides a multimode communication terminal which contains at least a first separate channel module and a second separate channel module. The multimode communication terminal can be configured to communicate by using the first channel module and/or the second channel module. The channel modules communicate according to different communication protocols. The multimode communication terminal further comprises: channel switch layer means for switching the first channel module to have parameter characteristics consistent with those of the second channel module, so that the multimode communication terminal enables the MIMO operation mode by using the first channel module and the second channel module at the same time. The present invention further provides a method for enabling a MIMO operation mode in a multimode communication terminal.

Abstract: One embodiment of the present invention provides a system that performs lithography verification for a double-patterning process on a mask layout without performing a full contour simulation of the mask layout. During operation, the system starts by receiving a first mask which is used in a first lithography step of the double-patterning process, and a second mask which is used in a second lithography step of the double-patterning process. Note that the first mask and the second mask are obtained by partitioning the mask layout. Next, the system receives an evaluation point on the mask layout. The system then determines whether the evaluation point is exclusively located on a polygon of the first mask, exclusively located on a polygon of the second mask, or located elsewhere. The system next computes a printing indicator at the evaluation point for the mask layout based on whether the evaluation point is exclusively located on a polygon of the first mask or exclusively located on a polygon of the second mask.