Patents by Inventor Hua Sun
Hua Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180105851Abstract: The present invention provides a method and a system for preparing pulp for paper with grass straws as raw material. The method of the present invention includes the following steps: 1) adding water in raw material for pulping, performing a first enzymolysis with ligninolytic enzyme; 2) cooking the first enzymolysis product at 80-130° C.; 3) performing second enzymolysis with hemicellulase to the cooked product. The method of the present invention is able to improve the pulp yield, reduce discharge of pollutants from black liquor, lower alkali consumption and energy consumption, and facilitate extraction of lignin and C-5 sugars, and pulp has a high quality.Type: ApplicationFiled: May 24, 2017Publication date: April 19, 2018Inventors: HUA SUN, ZHONGYU LIU
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Patent number: 9880966Abstract: Application-specific tailoring and reuse of a platform for a target integrated circuit may include determining, using a processor, a plurality of unused interfaces of the platform and determining, using the processor, connectivity of a circuit block to be coupled to the platform within the target integrated circuit. The method may include coupling, using the processor, the circuit block to the platform using an interface that is compatible with the circuit block and selected from the plurality of unused interfaces of the platform.Type: GrantFiled: September 3, 2015Date of Patent: January 30, 2018Assignee: XILINX, INC.Inventors: L. James Hwang, Vinod K. Kathail, Sundararajarao Mohan, Jorge E. Carrillo, Hua Sun
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Publication number: 20180011814Abstract: A motherboard module having switchable PCI-E lanes includes a CPU, a first PCI-E slot, a second PCI-E slot, a first switch, and a second switch. 1st to a-th processor pin sets of the CPU are switchably electrically connected to 1st to a-th first PCI-E pin sets of the first PCI-E slot or (2N?a+1)th to 2N-th second PCI-E pin sets of the second PCI-E slot via the first switch to form PCI-E lanes whose number is a. (a+1)-th to 2N-th processor pin sets of the CPU are connected to the second input terminal of the second switch, and the second output terminal of the second switch is switchably electrically connected to (a+1)-th to 2N-th first PCI-E pin sets of the first PCI-E slot or 1st to (2N?a)th second PCI-E pin sets of the second PCI-E slot to form PCI-E lanes whose number is 2N?a, wherein 1<a<2N.Type: ApplicationFiled: September 2, 2016Publication date: January 11, 2018Applicant: GIGA-BYTE TECHNOLOGY CO.,LTD.Inventors: Pei-Hua Sun, Hon-Yeh Lee, Yen-Yun Chang
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Publication number: 20180011713Abstract: A BIOS control method for PCI-E lanes includes the following steps. A BIOS obtains information of whether a first expansion card and a second expansion card are respectively inserted in a first PCI-E slot and a second PCI-E slot, and if the second expansion card is inserted in the second PCI-E slot, then the BIOS instructs a CPU to reverse the order of PCI-E lanes electrically connected between the CPU and the second PCI-E slot.Type: ApplicationFiled: September 2, 2016Publication date: January 11, 2018Applicant: GIGA-BYTE TECHNOLOGY CO.,LTD.Inventors: Pei-Hua Sun, Yen-Yun Chang, Weiyuan Cheng
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Patent number: 9805152Abstract: In an example implementation, a method is provided for compiling an HLL source file including function calls to one or more hardware accelerated functions. Function calls in the HLL source file to hardware accelerated functions are identified and grouped into a plurality of subsets for exclusive implementation in programmable logic resources. Sets of configuration data are generated for configuration of the programmable logic resources to implement hardware accelerated functions for the respective subsets of function calls. An interface manager is generated and the identified function calls are replaced with interface code configured to communicate with the interface manager. The interface manager manages configuration of the programmable logic resources to switch between the sets of configuration data to implement hardware accelerated functions for different ones of the subsets.Type: GrantFiled: February 17, 2016Date of Patent: October 31, 2017Assignee: XILINX, INC.Inventors: Jorge E. Carrillo, Vinod K. Kathail, L. James Hwang, Sundararajarao Mohan, Hua Sun
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Patent number: 9652570Abstract: Implementing a system-on-chip (SOC) design specified as a high level programming language (HLL) application may include querying, using a computer, a platform description to determine an available interface of a platform for a target integrated circuit and generating, using the computer, hardware for a function of the HLL application marked for hardware acceleration and hardware coupling the marked function with the available interface of the platform. Implementing the SOC design may also include modifying, using the computer, the HLL application with program code configured to access the generated hardware for the marked function and building, using the computer, the hardware and the software of the SOC design.Type: GrantFiled: September 3, 2015Date of Patent: May 16, 2017Assignee: XILINX, INC.Inventors: Vinod K. Kathail, L. James Hwang, Sundararajarao Mohan, Jorge E. Carrillo, Hua Sun, Tom Shui, Yogesh L. Chobe
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Patent number: 9631196Abstract: The present invention relates to the application of isolated promoters and synthetic dominant selection constructs and enhancers for gene targeting for efficient production of genetically modified cells in a species selected from the Pucciniomycotina and Ustilaginomycotina subphyla, in particular, species selected from the Rhodosporidium, Sporisorium, Sporobolomyces or Ustilago genera.Type: GrantFiled: May 10, 2012Date of Patent: April 25, 2017Assignee: TEMASEK LIFE SCIENCES LABORATORY LIMITEDInventors: Liang Hui Ji, Yan Bin Liu, John Chong Mei Koh, Long Hua Sun
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Publication number: 20170011419Abstract: A mechanism is provided for personalizing a user's E-commerce environment. Identified lifecycle state transactions associated with the user are modeled by performing a lifecycle state transition probability calculation utilizing collected social media data and transaction data. Utilizing the model of the identified lifecycle state transactions, a two-level Hidden Markov Model (HMM) lifecycle model is generated for current lifecycle states being experienced by the user. Utilizing the two-level HMM lifecycle model for current lifecycle states being experienced by the user, one or more future behavioral predictions are generated with regard to the user's lifecycle. One or more E-commerce recommendations are then issued to the user based on the one or more future behavioral predictions.Type: ApplicationFiled: July 9, 2015Publication date: January 12, 2017Inventors: Ke Ke Cai, Dong Xu Duan, Zhong Su, Chang Hua Sun, Shi Lei Zhang, Shi Wan Zhao
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Publication number: 20160199355Abstract: The present disclosure is generally directed to antiviral compounds, and more specifically directed to combinations of compounds which can inhibit the function of the NS5A protein encoded by Hepatitis C virus (HCV), compositions comprising such combinations, and methods for inhibiting the function of the NS5A protein.Type: ApplicationFiled: March 11, 2016Publication date: July 14, 2016Inventors: PIYASENA HEWAWASAM, JOHN F. KADOW, OMAR D. LOPEZ, NICHOLAS A. MEANWELL, YONG TU, ALAN XIANGDONG WANG, NINGNING XU, SAMAYAMUNTHULA VENKATA SATYA ARUN KUMAR GUPTA, POTHUKANURI SRINIVASU, INDASI GOPI KUMAR, PONUGUPATI SURESH KUMAR, MAKONEN BELEMA, ROBERT A. FRIDELL, MIN GAO, JULIE A. LEMM, DONALD R. O'BOYLE, II, JIN-HUA SUN, CHUNFU WANG, YING-KAI WANG
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Patent number: 9326973Abstract: The present disclosure is generally directed to antiviral compounds, and more specifically directed to combinations of compounds which can inhibit the function of the NS5A protein encoded by Hepatitis C virus (HCV), compositions comprising such combinations, and methods for inhibiting the function of the NS5A protein.Type: GrantFiled: January 7, 2013Date of Patent: May 3, 2016Assignee: Bristol-Myers Squibb CompanyInventors: Piyasena Hewawasam, John F. Kadow, Omar D. Lopez, Nicholas A. Meanwell, Yong Tu, Alan Xiangdong Wang, Ningning Xu, Samayamunthula Venkata Satya Arun Kumar Gupta, Pothukanuri Srinivasu, Indasi Gopi Kumar, Ponugupati Suresh Kumar, Makonen Belema, Robert A. Fridell, Min Gao, Julie A. Lemm, Donald R. O'Boyle, II, Jin-Hua Sun, Chunfu Wang, Ying-Kai Wang
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Patent number: 9223921Abstract: In an example implementation, a method is provided for compiling an HLL source file. The HLL source file checked for function calls to a set of hardware-accelerated functions having hardware implementations specified in a hardware library. For each HLL function call to a hardware-accelerated function, a circuit design is retrieved from the hardware library. The circuit design specifies a hardware implementation of the hardware-accelerated function. HLL interface code configured to communicate with the hardware implementation of the hardware-accelerated function is also generated. The HLL function call to the hardware-accelerated function in the HLL source file is replaced with the generated interface code. The HLL source file is compiled to generate a program executable on a processor of a programmable IC. Configuration data is generated that implements the retrieved circuit designs on the programmable circuitry of the programmable IC.Type: GrantFiled: November 13, 2014Date of Patent: December 29, 2015Assignee: XILINX, INC.Inventors: Jorge E. Carrillo, L. James Hwang, Hua Sun, Sundararajarao Mohan, Vinod K. Kathail
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Patent number: 9147024Abstract: Hardware and software co-synthesis performance estimation includes, for a design specified in a high level programming language and having a processor executable partition and a partition selected for hardware acceleration, estimating hardware latency for a hardware accelerator implementation of the selected partition, scheduling the selected partition using the hardware latency generating hardware partition latency information, and compiling an instrumented version of the design using a processor. The instrumented and compiled version of the design is executed generating software latency information. A design performance for the design is determined through combining the hardware partition latency information with the software latency information.Type: GrantFiled: November 6, 2014Date of Patent: September 29, 2015Assignee: XILINX, INC.Inventors: Vinod K. Kathail, Hua Sun, Sundararajarao Mohan, L. James Hwang, Yogesh L. Chobe
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Publication number: 20150183140Abstract: A foam grip fabrication method includes a mold preparation step to prepare a foaming mold having a size reduced to a predetermined foaming ratio, a heating step to heat the foaming mold to a bridging curve temperature, and then to close the foaming mold and to draw the foaming mold to a negative pressure state, a material filling step to mix a raw material to be foamed with a foaming agent and a crosslinking agent and then to inject the foaming material thus obtained into the foaming mold, and a foaming step to open the foaming mold after vulcanization of the molding for enabling a flow of outside air to enter and to cause the molding thus molded to expand and then to put the molding on a tool for cooling and shaping so that a finished product in the desired size is thus obtained.Type: ApplicationFiled: May 28, 2014Publication date: July 2, 2015Applicant: FEELTECGRIP INC.Inventor: Chi-Hua SUN
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Patent number: 9003433Abstract: Business application logic corresponding to a business is generated according to requirements of the business. The business application logic includes Web services and Widgets. The Widgets in the business application logic are mashed up to create a Widget mashup application. An adaptation relationship is established between the Web services and the Widgets in the Widget mashup application. An executable business process is generated for the business based on the business application logic and the adaptation relationship. An executable mashup Widget application is generated based on the Widget mashup application and the adaptation relationship.Type: GrantFiled: January 23, 2012Date of Patent: April 7, 2015Assignee: International Business Machines CorporationInventors: Shuang Liang, Xiao Xing Liang, Xin Peng Liu, Chang Hua Sun, Xi Ning Wang, Liang Xue, Yu Chen Zhou
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Patent number: 8972711Abstract: A CPU core unlocking device applied to a computer system is provided. The core unlocking device includes a CPU having a plurality of signal terminals and a core unlocking executing unit having a plurality of GPIO ports connected with the corresponding signal terminals of the CPU. The GPIO ports of the core unlocking executing unit generate and transmit and transmit a combination of core unlocking signal to the signal terminals of the CPU to unlock the CPU core.Type: GrantFiled: March 3, 2011Date of Patent: March 3, 2015Assignee: ASUSTeK Computer Inc.Inventors: Pei-Hua Sun, Pai-Ching Huang, Yi-Min Huang, Meng-Hsiung Lee, Nan-Kun Lo
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Patent number: 8947862Abstract: An expansion card module includes a box, a tray, a circuit board, and an interconnection device. The box is disposed in a drive bay on the front of a case of a computer. The tray is movably installed in the box and has a slide mechanism. The tray slides into or out of the box by the slide mechanism. The circuit board is disposed on the tray and has a first expansion slot. An expansion card electrically inserts into the first expansion slot of the circuit board, and the circuit board is electrically connected to the motherboard of computer through the interconnection device.Type: GrantFiled: February 7, 2013Date of Patent: February 3, 2015Assignee: Giga-Byte Technology Co., Ltd.Inventor: Pei Hua Sun
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Patent number: 8935276Abstract: A method and apparatus for handling data analysis. The apparatus includes an editing device which adds user-specified one of a plurality of operation units to a user-specified layer in a data analysis in response to a user operation, each of the operation units performing a predetermined processing on an associated data source, a connecting device which connects at least one user-specified operation unit in the data analysis to an analysis path in response to a user operation, and a user interface. The user interface receives the user operations and displays the data analysis by representing layers in the data analysis, operation units in the layers and connections on the analysis path in a visual manner.Type: GrantFiled: June 29, 2011Date of Patent: January 13, 2015Assignee: International Business Machines CorporationInventors: Shao Chun Li, Xiao Hua Sun, Qiang Zhang
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Patent number: 8878489Abstract: An estimation method for residual discharging time of batteries includes the steps of: providing a set of battery-discharge-current intervals and a set of battery-discharge equations, setting the discharge time of each battery-discharge-current intervals at zero; detecting a discharge current, voltage and time of batteries; judging whether the discharge current exceeds all of the battery-discharge-current intervals; selecting one of the battery-discharge-current intervals and the associated battery-discharge equation according to the detected discharge current; calculating an estimation of residual discharging time; accumulating and recording the discharge time; judging whether the discharge voltage is lower than a predetermined value and calculating an estimation error of the residual discharging time; and adjusting parameters of the battery-discharge equation for reducing the estimation error of the residual discharging time if the estimation error is greater than a predetermined error value.Type: GrantFiled: November 18, 2010Date of Patent: November 4, 2014Assignee: Ablerex Electronics Co., Ltd.Inventors: Hung-Liang Chou, Yu-Hua Sun, Chin-Chang Wu, Wen-Jung Chiang
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Publication number: 20140244646Abstract: A method, apparatus and system for processing webpage data. The method includes: in response to a webpage being opened, sending a link contained in the webpage to a network side device; receiving a group identification from the network side device, the group identification being determined by the network side device according to the link and used to specify a group the link belongs to; determining whether there is a browsed link belonging to the group specified by the group identification; and in response to determining there is a browsed link belonging to the group specified by the group identification, prompting that webpage content pointed by the link contained in the webpage has been browsed.Type: ApplicationFiled: February 24, 2014Publication date: August 28, 2014Applicant: International Business Machines CorporationInventors: Sheng Hua Bao, Dong Xu Duan, Wei Hong Qian, Chang Hua Sun
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Publication number: 20140185208Abstract: An expansion card module includes a box, a tray, a circuit board, and an interconnection device. The box is disposed in a drive bay on the front of a case of a computer. The tray is movably installed in the box and has a slide mechanism. The tray slides into or out of the box by the slide mechanism. The circuit board is disposed on the tray and has a first expansion slot. An expansion card electrically inserts into the first expansion slot of the circuit board, and the circuit board is electrically connected to the motherboard of computer through the interconnection device.Type: ApplicationFiled: February 7, 2013Publication date: July 3, 2014Applicant: GIGA-BYTE TECHNOLOGY CO., LTD.Inventor: Pei Hua Sun