Abstract: A key press detecting circuit for detecting the status of the key is provided. The key press detecting circuit comprises a discharging circuit which discharges when the key (K1) is pressed; and a voltage detecting circuit, which comprises a combination of a PNP transistor (T2) and a NPN transistor (T3), wherein when the discharging circuit discharges for a predefined period, the PNP transistor (T2) will be turn on, which causes the NPN transistor (T3) to be turned on and to output a second signal for a second function.

Abstract: A method and apparatus for handling data analysis. The apparatus includes an editing device which adds user-specified one of a plurality of operation units to a user-specified layer in a data analysis in response to a user operation, each of the operation units performing a predetermined processing on an associated data source, a connecting device which connects at least one user-specified operation unit in the data analysis to an analysis path in response to a user operation, and a user interface. The user interface receives the user operations and displays the data analysis by representing layers in the data analysis, operation units in the layers and connections on the analysis path in a visual manner.

Abstract: An estimation method for residual discharging time of batteries includes the steps of: providing a set of battery-discharge-current intervals and a set of battery-discharge equations, setting discharge time of each battery-discharge-current intervals zero; detecting a discharge current, voltage and time of batteries; judging whether the discharge current exceeding all of the battery-discharge-current intervals; selecting one of the battery-discharge-current intervals and the associated battery-discharge equation according to the detected discharge current; calculating an estimation of residual discharging time; accumulating and recording the discharge time; judging whether the discharge voltage being lower than a predetermined value and calculating an estimation error of the residual discharging time; adjusting parameters of the battery-discharge equation for reducing the estimation error of the residual discharging time if the estimation error is greater than a predetermined error value.

Abstract: A process for producing a gaseous component of air under pressure by cryogenic separation is provided.

Abstract: A protection circuit for a central processing unit (CPU) is provided. The protection circuit has a detecting unit and an enable switch. The detecting unit detects whether the short is occurred or not between a power pin of the CPU and the ground end before providing a system voltage to the CPU. The enable switch is coupled to the detecting unit. The enable switch determines whether to provide the system voltage to the power pin of the CPU according to the detecting result of the detecting unit. When the short is occurred between the power pin of the CPU and the ground end, the enable switch turning off for cutting off the system voltage from being provided to the CPU and prevents an electronic device including the CPU from booting.

Abstract: A three-leg power converter apparatus including first, second and third input/output ports, a three-leg bridge converter, a filter circuit, a decoupling circuit and a controller is presented. The three-leg bridge converter has three single-leg circuits, two DC terminals connecting to two terminals of the first input/output port, and three mid-terminals with each of them being formed by a middle point of one of the three single-leg circuits. The controller connects to the three-leg bridge converter for controlling an input or output current passing through each DC terminal and mid-terminal. The filter circuit connects between two of the mid-terminals and the second input/output port. The decoupling circuit has two terminals connecting to the second input/output port and another terminal connecting to a terminal of the third input/output port, with the third input/output port having another terminal connecting to the other mid-terminal that dose not connect with the filter circuit.

Abstract: A CPU core unlocking device applied to a computer system is provided. The core unlocking device includes a CPU having a plurality of signal terminals and a core unlocking executing unit having a plurality of GPIO ports connected with the corresponding signal terminals of the CPU. The GPIO ports of the core unlocking executing unit generate and transmit and transmit a combination of core unlocking signal to the signal terminals of the CPU to unlock the CPU core.

Abstract: A computer has a first BIOS unit, a second BIOS unit, a bus, a detecting unit, and a first delay unit. The detecting unit is connected to the bus, the first BIOS unit, and the second BIOS unit operationally. In addition, the first delay unit is electrically connected to the detecting unit for controlling the detecting unit to check a status of a bus signal on the bus after a predetermined delay time. Accordingly, the detecting unit may enable the first BIOS unit or the second BIOS unit to boot the computer system according to the state of the bus signal.

Abstract: An exemplary lateral diffused metal oxide semiconductor device includes a first-type substrate, a gate oxide film disposed on the first-type substrate, a poly gate disposed on the gate oxide film, a first second-type slightly doped region formed in the first-type substrate and acting as a well, a first first-type highly doped region formed in the well and acting as a body, a first second-type highly doped region formed in the body and acting as a source, a second second-type highly doped region formed in the well and acting as a drain, a second first-type highly doped region formed in the body, and a first first-type doped region formed in the body and is beneath the source.

Abstract: A computer system includes a casing with a front end and a back end, a first opening formed on the front end of the casing, a second opening formed on the back end of the casing and an electronic component with connecting ports. The connecting ports of the peripheral electronic component expose from one of the first opening and the second opening.

Abstract: A motherboard which can play an image or a video in a power-off state is disclosed. The motherboard includes a circuit board, a north bridge chipset, a digital photo frame chipset, and a switch unit. The north bridge chipset, the digital photo frame chipset, and the switch unit are disposed on the circuit board. The digital photo frame chipset is activated according to a stand-by power in the power-off state. The switch unit is electrically connected with the north bridge chipset and the digital photo frame chipset, respectively. The switch unit electrically communicates with the north bridge chipset or the digital photo frame chipset according to a triggering signal. The motherboard may utilize the stand-by power in the power-off state to display an image by a display device via the digital photo frame chipset and the north bridge chipset when a computer system is powered off.

Abstract: A motherboard capable of detecting consumed power and a method for detecting consumed power thereof are provided. The motherboard includes a VCC layer, a plurality of resistance elements, and a detecting module. A plurality of power traces are laid at the VCC layer, and each of the power traces conducts an operating voltage, respectively. The resistance elements are laid at sources of each of the power traces, respectively. The detecting module is coupled with each of the resistance elements, respectively, to obtain a current value of a current flowing through each of the resistance elements, and generates consumed power corresponding to each of the operating voltages according to the current value and the operating voltage corresponding to the current value.

Abstract: A three-leg power converter apparatus including first, second and third input/output ports, a three-leg bridge converter, a filter circuit, a decoupling circuit and a controller is presented. The three-leg bridge converter has three single-leg circuits, two DC terminals connecting to two terminals of the first input/output port, and three mid-terminals with each of them being formed by a middle point of one of the three single-leg circuits. The controller connects to the three-leg bridge converter for controlling an input or output current passing through each DC terminal and mid-terminal. The filter circuit connects between two of the mid-terminals and the second input/output port. The decoupling circuit has two terminals connecting to the second input/output port and another terminal connecting to a terminal of the third input/output port, with the third input/output port having another terminal connecting to the other mid-terminal that dose not connect with the filter circuit.

Abstract: A computer system includes a clock generator, a system chipset, a controller and a multiplexing unit. The clock generator generates a reference clock according to a plurality of setting values in a frequency setting table. The system chipset generates a piece of first clock control information and a first clock. The controller is used to switch the level of the control signal and generates a piece of second clock control information and a second clock. The multiplexing unit is used to receive the control signal to select either the first clock control information or the second clock control information to be a piece of main clock control information and select either the first clock or the second clock to be a main clock. The clock generator adjusts the setting values according to the main clock control information and the main clock to change the frequency of the reference clock.

Abstract: A computer system includes a triggering device; and a motherboard, connected to the triggering device, further comprising: a memory stored with a setting parameter of a basic-input-output-system; and a counter connected between the triggering device and the memory; wherein an erasing signal, for erasing the memory, is outputted to the memory from the counter according to a triggering signal outputted from the triggering device while a boosting procedure cannot be successfully executed by the computer system.

Abstract: A power saving system is provided, comprising a system chip, at least one controller and at least one corresponding switch. The system chip is coupled to the controller. The controller is coupled between the system chip and a connector. The switch is coupled between the controller and a power and is turned on or off according to a GPIO signal. When the switch is turned on, the controller is active. When there is no device through the connector and the controller coupled to the system chip, the controller is turned off for power saving.

Abstract: A key press detecting circuit for detecting the status of the key is provided. The key press detecting circuit comprises a discharging circuit which discharges when the key (K1) is pressed; and a voltage detecting circuit, which comprises a combination of a PNP transistor (T2) and a NPN transistor (T3), wherein when the discharging circuit discharges for a predefined period, the PNP transistor (T2) will be turn on, which causes the NPN transistor (T3) to be turned on and to output a second signal for a second function.

Abstract: A motherboard, a method for recovering a BIOS thereof, and a method for booting a computer are provided. In the method for booting the computer, a first boot block of a first BIOS unit is executed first, and then a second boot block of a second BIOS unit is executed. Afterwards, BIOS main program codes of the second BIOS unit are executed. When the second BIOS unit is down, a recovery mechanism of the first boot block is used to overwrite data in the second BIOS unit with a backup file.

Abstract: A computer has a first BIOS unit, a second BIOS unit, a bus, a detecting unit, and a first delay unit. The detecting unit is connected to the bus, the first BIOS unit, and the second BIOS unit operationally. In addition, the first delay unit is electrically connected to the detecting unit for controlling the detecting unit to check a status of a bus signal on the bus after a predetermined delay time. Accordingly, the detecting unit may enable the first BIOS unit or the second BIOS unit to boot the computer system according to the state of the bus signal.

Abstract: An exemplary lateral diffused metal oxide semiconductor device includes a first-type substrate, a gate oxide film disposed on the first-type substrate, a poly gate disposed on the gate oxide film, a first second-type slightly doped region formed in the first-type substrate and acting as a well, a first first-type highly doped region formed in the well and acting as a body, a first second-type highly doped region formed in the body and acting as a source, a second second-type highly doped region formed in the well and acting as a drain, a second first-type highly doped region formed in the body, and a first fist-type doped region formed in the body and is beneath the source.