Patents by Inventor Hua-Tai Lin
Hua-Tai Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961738Abstract: In a method of forming a pattern, a first pattern is formed over an underlying layer, the first pattern including main patterns and a lateral protrusion having a thickness of less than 25% of a thickness of the main patterns, a hard mask layer is formed over the first pattern, a planarization operation is performed to expose the first pattern without exposing the lateral protrusion, a hard mask pattern is formed by removing the first pattern while the lateral protrusion being covered by the hard mask layer, and the underlying layer is patterned using the hard mask pattern as an etching mask.Type: GrantFiled: February 12, 2021Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Ta Chen, Hua-Tai Lin, Han-Wei Wu, Jiann-Yuan Huang
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Publication number: 20240105518Abstract: A first group of semiconductor fins are over a first region of a substrate, the substrate includes a first stepped profile between two of the first group of semiconductor fins, and the first stepped profile comprises a first lower step, two first upper steps, and two first step rises extending from opposite sides of the first lower step to the first upper steps. A second group of semiconductor fins are over a second region of the substrate, the substrate includes a second stepped profile between two of the second group of semiconductor fins, and the second stepped profile comprises a second lower step, two second upper steps, and two second step rises extending from opposite sides of the second lower step to the second upper steps, in which the second upper steps are wider than the first upper steps in the cross-sectional view.Type: ApplicationFiled: January 11, 2023Publication date: March 28, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Ta CHEN, Han-Wei WU, Yuan-Hsiang LUNG, Hua-Tai LIN
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Publication number: 20240030073Abstract: In a method of patterning an integrated circuit, test layer thickness variation data is received when a test layer with a known thickness disposed over a test substrate undergoes tilted angle plasma etching. Overlay offset data per substrate locations caused by the tilted angle plasma etching is determined. The overlay offset data is determined based on the received thickness variation data. The overlay offset data is associated with an overlay between first circuit patterns of a first layer on the semiconductor substrate and corresponding second circuit patterns of a second layer disposed over the first layer on the substrate. A location of the substrate is adjusted based on the overlay offset data during a lithography operation to pattern a resist layer over the second layer. The second layer is patterned based on the projected layout patterns of the reticle and using the tilted angle plasma etching.Type: ApplicationFiled: July 19, 2023Publication date: January 25, 2024Inventors: Wei-De HO, Pei-Sheng Tang, Han-Wei Wu, Yuan-Hsiang Lung, Hua-Tai Lin, Chen-Jung Wang
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Patent number: 11846881Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, a photo catalytic layer disposed on the capping layer, and an absorber layer disposed on the photo catalytic layer and carrying circuit patterns having openings. Part of the photo catalytic layer is exposed at the openings of the absorber layer, and the photo catalytic layer includes one selected from the group consisting of titanium oxide (TiO2), tin oxide (SnO), zinc oxide (ZnO) and cadmium sulfide (CdS).Type: GrantFiled: July 27, 2022Date of Patent: December 19, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Huang Chen, Chi-Yuan Sun, Hua-Tai Lin, Hsin-Chang Lee, Ming-Wei Chen
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Publication number: 20230402277Abstract: A method includes depositing a dielectric layer over a semiconductor substrate; forming a first photoresist layer over the dielectric layer; patterning the first photoresist layer to form through holes, such that a first portion of the first photoresist layer between a first one and a second one of the through holes has a less height than a second portion of the first photoresist layer between the first one and a third one of the through holes; forming a spacer on the first portion of the first photoresist layer; performing an etching process on the dielectric layer to form via holes while the spacer remains covering the first portion of the first photoresist layer; forming a plurality of metal vias in the via holes.Type: ApplicationFiled: June 12, 2022Publication date: December 14, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Ta CHEN, Han-Wei WU, Yuan-Hsiang LUNG, Hua-Tai LIN
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Patent number: 11804410Abstract: A method for evaluation of thin film non-uniform stress using high order wafer warpage, the steps including measuring a net wafer warpage across a wafer area due to thin film deposition, fitting a two dimensional low-order polynomial to the wafer warpage measurements and subtracting the low-order polynomial from the net wafer warpage across the wafer area.Type: GrantFiled: March 5, 2020Date of Patent: October 31, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-De Ho, Han-Wei Wu, Pei-Sheng Tang, Meng-Jung Lee, Hua-Tai Lin, Szu-Ping Tung, Lan-Hsin Chiang
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Publication number: 20230298901Abstract: A method for forming a semiconductor structure includes forming a pattern having first and second line features extending in a first direction on a substrate. After depositing a photoresist layer on the substrate to cover the pattern, the photoresist layer is patterned to form a cut pattern including first and second cut features exposing portions of the respective first and second line features. In a top view, at least one of the first and second cut features is asymmetrically arranged with respect to a central axis of a corresponding first or second line feature. At least one angled ion implantation is performed to enlarge the first and second cut features in at least one direction perpendicular to the first direction. The portions of the first and second line features exposed by the respective first and second cut features are then removed.Type: ApplicationFiled: May 30, 2023Publication date: September 21, 2023Inventors: Tzung-Hua LIN, Yi-Ko CHEN, Chia-Chu LIU, Hua-Tai LIN
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Patent number: 11749570Abstract: In a method of patterning an integrated circuit, test layer thickness variation data is received when a test layer with a known thickness disposed over a test substrate undergoes tilted angle plasma etching. Overlay offset data per substrate locations caused by the tilted angle plasma etching is determined. The overlay offset data is determined based on the received thickness variation data. The overlay offset data is associated with an overlay between first circuit patterns of a first layer on the semiconductor substrate and corresponding second circuit patterns of a second layer disposed over the first layer on the substrate. A location of the substrate is adjusted based on the overlay offset data during a lithography operation to pattern a resist layer over the second layer. The second layer is patterned based on the projected layout patterns of the reticle and using the tilted angle plasma etching.Type: GrantFiled: August 31, 2021Date of Patent: September 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-De Ho, Pei-Sheng Tang, Han-Wei Wu, Yuan-Hsiang Lung, Hua-Tai Lin, Chen-Jung Wang
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Patent number: 11748549Abstract: Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.Type: GrantFiled: April 21, 2021Date of Patent: September 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Min Huang, Bo-Han Chen, Cherng-Shyan Tsay, Chien-Wen Lai, Hua-Tai Lin, Chia-Cheng Chang, Lun-Wen Yeh, Shun-Shing Yang
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Patent number: 11688610Abstract: A method for forming a semiconductor structure includes forming a pattern having first and second line features extending in a first direction on a substrate. After depositing a photoresist layer on the substrate to cover the pattern, the photoresist layer is patterned to form a cut pattern including first and second cut features exposing portions of the respective first and second line features. In a top view, at least one of the first and second cut features is asymmetrically arranged with respect to a central axis of a corresponding first or second line feature. At least one angled ion implantation is performed to enlarge the first and second cut features in at least one direction perpendicular to the first direction. The portions of the first and second line features exposed by the respective first and second cut features are then removed.Type: GrantFiled: March 3, 2021Date of Patent: June 27, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tzung-Hua Lin, Yi-Ko Chen, Chia-Chu Liu, Hua-Tai Lin
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Publication number: 20230139799Abstract: In pattern formation method, a photomask is loaded into a lithography apparatus, an exposure light is applied to a photo resist layer formed over a substrate through or via the photomask, and the photo resist layer is developed. The photomask includes a plurality of octagonal shape patterns periodically arranged in a first direction and a second direction crossing the first direction. A width Lx of horizontal sides extending in the first direction of each of the plurality octagonal shape patterns is different from a width Ly of vertical sides extending in the second direction of each of the plurality octagonal shape patterns.Type: ApplicationFiled: March 30, 2022Publication date: May 4, 2023Inventors: Wei-De HO, Han-Wei WU, Yuan-Hsiang LUNG, Hua-Tai LIN
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Publication number: 20230067049Abstract: A method for manufacturing a memory device includes forming a dielectric layer over a wafer, wherein the wafer has a device region and a peripheral region adjacent to the device region. A bottom via opening is formed in the dielectric layer and over the device region of the wafer and a trench is fanned in the dielectric layer and over the peripheral region of the wafer. A bottom electrode via is formed in the bottom via opening. A bottom electrode layer is conformally formed over the bottom electrode via and lining a sidewall and a bottom of the trench. A memory layer and a top electrode are formed over the bottom electrode layer.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pei-Sheng TANG, Wei-De HO, Han-Wei WU, Yuan-Hsiang LUNG, Hua-Tai LIN
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Publication number: 20230062426Abstract: In a method of patterning an integrated circuit, test layer thickness variation data is received when a test layer with a known thickness disposed over a test substrate undergoes tilted angle plasma etching. Overlay offset data per substrate locations caused by the tilted angle plasma etching is determined. The overlay offset data is determined based on the received thickness variation data. The overlay offset data is associated with an overlay between first circuit patterns of a first layer on the semiconductor substrate and corresponding second circuit patterns of a second layer disposed over the first layer on the substrate. A location of the substrate is adjusted based on the overlay offset data during a lithography operation to pattern a resist layer over the second layer. The second layer is patterned based on the projected layout patterns of the reticle and using the tilted angle plasma etching.Type: ApplicationFiled: August 31, 2021Publication date: March 2, 2023Inventors: Wei-De HO, Pei-Sheng TANG, Han-Wei WU, Yuan-Hsiang LUNG, Hua-Tai LIN, Chen-Jung WANG
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Publication number: 20230049896Abstract: A method of manufacturing a semiconductor device includes forming an underlying structure in a first area and a second area over a substrate. A first layer is formed over the underlying structure. The first layer is removed from the second area while protecting the first layer in the first area. A second layer is formed over the first area and the second area, wherein the second layer has a smaller light transparency than the first layer. The second layer is removed from the first area, and first resist pattern is formed over the first layer in the first area and a second resist pattern over the second layer in the second area.Type: ApplicationFiled: April 5, 2022Publication date: February 16, 2023Inventors: Jin-Dah CHEN, Han-Wei WU, Yuan-Hsiang LUNG, Hua-Tai LIN
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Patent number: 11543753Abstract: In one example, an apparatus includes an extreme ultraviolet illumination source and an illuminator. The extreme ultraviolet illumination source is arranged to generate a beam of extreme ultraviolet illumination to pattern a resist layer on a substrate. The illuminator is arranged to direct the beam of extreme ultraviolet illumination onto a surface of a photomask. In one example, the illuminator includes a field facet mirror and a pupil facet mirror. The field facet mirror includes a first plurality of facets arranged to split the beam of extreme ultraviolet illumination into a plurality of light channels. The pupil facet mirror includes a second plurality of facets arranged to direct the plurality of light channels onto the surface of the photomask. The distribution of the second plurality of facets is denser at a periphery of the pupil facet mirror than at a center of the pupil facet mirror.Type: GrantFiled: May 28, 2020Date of Patent: January 3, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ken-Hsien Hsieh, Shih-Ming Chang, Wen Lo, Wei-Shuo Su, Hua-Tai Lin
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Publication number: 20220373876Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, a photo catalytic layer disposed on the capping layer, and an absorber layer disposed on the photo catalytic layer and carrying circuit patterns having openings. Part of the photo catalytic layer is exposed at the openings of the absorber layer, and the photo catalytic layer includes one selected from the group consisting of titanium oxide (TiO2), tin oxide (SnO), zinc oxide (ZnO) and cadmium sulfide (CdS).Type: ApplicationFiled: July 27, 2022Publication date: November 24, 2022Inventors: Ching-Huang CHEN, Chi-Yuan SUN, Hua-Tai LIN, Hsin-Chang LEE, Ming-Wei CHEN
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Publication number: 20220359313Abstract: A method for evaluation of thin film non-uniform stress using high order wafer warpage, the steps including measuring a net wafer warpage across a wafer area due to thin film deposition, fitting a two dimensional low-order polynomial to the wafer warpage measurements and subtracting the low-order polynomial from the net wafer warpage across the wafer area.Type: ApplicationFiled: July 25, 2022Publication date: November 10, 2022Inventors: Wei-De HO, Han-Wei WU, Pei-Sheng TANG, Meng-Jung LEE, Hua-Tai LIN, Szu-Ping TUNG, Lan-Hsin CHIANG
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Publication number: 20220328304Abstract: A patterning process is performed on a semiconductor wafer coated with a bottom layer, a middle layer and a photoresist layer having a starting thickness. The patterning process includes: performing an exposure step including exposing the semiconductor wafer using a mask that includes a feature which produces an intermediate light exposure in a target area followed by processing that creates openings in the photoresist layer in accordance with the mask and thins the photoresist in the target area due to the intermediate light exposure in the target area leaving thinned photoresist in the target area; performing middle layer etching to form openings in the middle layer aligned with the openings in the photoresist layer, wherein the middle layer etching does not remove the middle layer in the target area due to protection provided by the thinned photoresist; and performing trim etching to trim the middle layer in the target area.Type: ApplicationFiled: July 8, 2021Publication date: October 13, 2022Inventors: Kuo-Chang Kau, Wen-Yun Wang, Chia-Chu Liu, Hua-Tai Lin
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Patent number: 11448956Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, a photo catalytic layer disposed on the capping layer, and an absorber layer disposed on the photo catalytic layer and carrying circuit patterns having openings. Part of the photo catalytic layer is exposed at the openings of the absorber layer, and the photo catalytic layer includes one selected from the group consisting of titanium oxide (TiO2), tin oxide (SnO), zinc oxide (ZnO) and cadmium sulfide (CdS).Type: GrantFiled: September 5, 2019Date of Patent: September 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ching-Huang Chen, Chi-Yuan Sun, Hua-Tai Lin, Hsin-Chang Lee, Ming-Wei Chen
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Publication number: 20220262624Abstract: In a method of forming a pattern, a first pattern is formed over an underlying layer, the first pattern including main patterns and a lateral protrusion having a thickness of less than 25% of a thickness of the main patterns, a hard mask layer is formed over the first pattern, a planarization operation is performed to expose the first pattern without exposing the lateral protrusion, a hard mask pattern is formed by removing the first pattern while the lateral protrusion being covered by the hard mask layer, and the underlying layer is patterned using the hard mask pattern as an etching mask.Type: ApplicationFiled: February 12, 2021Publication date: August 18, 2022Inventors: Jin-Dah CHEN, Hua-Tai LIN, Han-Wei WU, Jiann-Yuan HUANG