Patents by Inventor Hua-Tai Lin
Hua-Tai Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11392745Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.Type: GrantFiled: November 30, 2020Date of Patent: July 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yun-Lin Wu, Cheng-Cheng Kuo, Chia-Ping Chiang, Chih-Wei Hsu, Hua-Tai Lin, Kuei-Shun Chen, Yuan-Hsiang Lung, Yan-Tso Tsai
-
Patent number: 11392045Abstract: A method for manufacturing a structure on a substrate includes projecting an image of a reference pattern onto a substrate having a first patterned layer, the first patterned layer including first alignment marks and first overlay measurement marks, and the reference pattern including second alignment marks and second overlay measurement marks, aligning, based on the first alignment marks and the second alignment marks, the first patterned layer to the image of the reference pattern, obtaining a pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks, and determining compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.Type: GrantFiled: December 7, 2020Date of Patent: July 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Yun Wang, Hua-Tai Lin, Chia-Chu Liu
-
Publication number: 20220102162Abstract: A method for forming a semiconductor structure includes forming a pattern having first and second line features extending in a first direction on a substrate. After depositing a photoresist layer on the substrate to cover the pattern, the photoresist layer is patterned to form a cut pattern including first and second cut features exposing portions of the respective first and second line features. In a top view, at least one of the first and second cut features is asymmetrically arranged with respect to a central axis of a corresponding first or second line feature. At least one angled ion implantation is performed to enlarge the first and second cut features in at least one direction perpendicular to the first direction. The portions of the first and second line features exposed by the respective first and second cut features are then removed.Type: ApplicationFiled: March 3, 2021Publication date: March 31, 2022Inventors: Tzung-Hua LIN, Yi-Ko CHEN, Chia-Chu LIU, Hua-Tai LIN
-
Publication number: 20210270751Abstract: In a method for inspecting pattern defects, a plurality of patterns are formed over an underlying layer. The plurality of patterns are electrically isolated from each other. A part of the plurality of patterns are scanned with an electron beam to charge the plurality of patterns. An intensity of secondary electrons emitted from the scanned part of the plurality of patterns is obtained. One or more of the plurality of patterns that show an intensity of the secondary electrons different from others of the plurality of patterns are searched.Type: ApplicationFiled: October 29, 2020Publication date: September 2, 2021Inventors: Ju-Ying CHEN, Che-Yen LEE, Chia-Fong CHANG, Hua-Tai LIN, Te-Chih HUANG, Chi-Yuan SUN, Jiann Yuan HUANG
-
Publication number: 20210240907Abstract: Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.Type: ApplicationFiled: April 21, 2021Publication date: August 5, 2021Inventors: Chin-Min Huang, Bo-Han Chen, Cherng-Shyan Tsay, Chien-Wen Lai, Hua-Tai Lin, Chia-Cheng Chang, Lun-Wen Yeh, Shun-Shing Yang
-
Publication number: 20210132504Abstract: In one example, an apparatus includes an extreme ultraviolet illumination source and an illuminator. The extreme ultraviolet illumination source is arranged to generate a beam of extreme ultraviolet illumination to pattern a resist layer on a substrate. The illuminator is arranged to direct the beam of extreme ultraviolet illumination onto a surface of a photomask. In one example, the illuminator includes a field facet mirror and a pupil facet mirror. The field facet mirror includes a first plurality of facets arranged to split the beam of extreme ultraviolet illumination into a plurality of light channels. The pupil facet mirror includes a second plurality of facets arranged to direct the plurality of light channels onto the surface of the photomask. The distribution of the second plurality of facets is denser at a periphery of the pupil facet mirror than at a center of the pupil facet mirror.Type: ApplicationFiled: May 28, 2020Publication date: May 6, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ken-Hsien HSIEH, Shih-Ming CHANG, Wen LO, Wei-Shuo SU, Hua-Tai LIN
-
Patent number: 10990744Abstract: Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.Type: GrantFiled: January 11, 2018Date of Patent: April 27, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Min Huang, Bo-Han Chen, Cherng-Shyan Tsay, Chien Wen Lai, Hua-Tai Lin, Chia-Cheng Chang, Lun-Wen Yeh, Shun-Shing Yang
-
Publication number: 20210088915Abstract: A method for manufacturing a structure on a substrate includes projecting an image of a reference pattern onto a substrate having a first patterned layer, the first patterned layer including first alignment marks and first overlay measurement marks, and the reference pattern including second alignment marks and second overlay measurement marks, aligning, based on the first alignment marks and the second alignment marks, the first patterned layer to the image of the reference pattern, obtaining a pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks, and determining compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.Type: ApplicationFiled: December 7, 2020Publication date: March 25, 2021Inventors: Wen-Yun WANG, Hua-Tai LIN, Chia-Chu LIU
-
Publication number: 20210089697Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.Type: ApplicationFiled: November 30, 2020Publication date: March 25, 2021Inventors: Yun-Lin Wu, Cheng-Cheng Kuo, Chia-Ping Chiang, Chih-Wei Hsu, Hua-Tai Lin, Kuei-Shun Chen, Yuan-Hsiang Lung, Yan-Tso Tsai
-
Publication number: 20210072633Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, a photo catalytic layer disposed on the capping layer, and an absorber layer disposed on the photo catalytic layer and carrying circuit patterns having openings. Part of the photo catalytic layer is exposed at the openings of the absorber layer, and the photo catalytic layer includes one selected from the group consisting of titanium oxide (TiO2), tin oxide (SnO), zinc oxide (ZnO) and cadmium sulfide (CdS).Type: ApplicationFiled: September 5, 2019Publication date: March 11, 2021Inventors: Ching-Huang CHEN, Chi-Yuan SUN, Hua-Tai LIN, Hsin-Chang LEE, Ming-Wei CHEN
-
Publication number: 20210066139Abstract: A method for evaluation of thin film non-uniform stress using high order wafer warpage, the steps including measuring a net wafer warpage across a wafer area due to thin film deposition, fitting a two dimensional low-order polynomial to the wafer warpage measurements and subtracting the low-order polynomial from the net wafer warpage across the wafer area.Type: ApplicationFiled: March 5, 2020Publication date: March 4, 2021Inventors: Wei-De HO, Han-Wei WU, Pei-Sheng TANG, Meng-Jung LEE, Hua-Tai LIN, Szu-Ping TUNG, Lan-Hsin CHIANG
-
Patent number: 10859924Abstract: A method for manufacturing a structure on a substrate includes projecting an image of a reference pattern onto a substrate having a first patterned layer, the first patterned layer including first alignment marks and first overlay measurement marks, and the reference pattern including second alignment marks and second overlay measurement marks, aligning, based on the first alignment marks and the second alignment marks, the first patterned layer to the image of the reference pattern, obtaining a pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks, and determining compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.Type: GrantFiled: April 27, 2018Date of Patent: December 8, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Yun Wang, Hua-Tai Lin, Chia-Chu Liu
-
Patent number: 10853552Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.Type: GrantFiled: May 6, 2019Date of Patent: December 1, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yun-Lin Wu, Cheng-Cheng Kuo, Chia-Ping Chiang, Chih-Wei Hsu, Hua-Tai Lin, Kuei-Shun Chen, Yuan-Hsiang Lung, Yan-Tso Tsai
-
Publication number: 20190258770Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.Type: ApplicationFiled: May 6, 2019Publication date: August 22, 2019Inventors: Yun-Lin Wu, Cheng-Cheng Kuo, Chia-Ping Chiang, Chih-Wei Hsu, Hua-Tai Lin, Kuei-Shun Chen, Yuan-Hsiang Lung, Yan-Tso Tsai
-
Publication number: 20190146357Abstract: A method for manufacturing a structure on a substrate includes projecting an image of a reference pattern onto a substrate having a first patterned layer, the first patterned layer including first alignment marks and first overlay measurement marks, and the reference pattern including second alignment marks and second overlay measurement marks, aligning, based on the first alignment marks and the second alignment marks, the first patterned layer to the image of the reference pattern, obtaining a pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks, and determining compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.Type: ApplicationFiled: April 27, 2018Publication date: May 16, 2019Inventors: Wen-Yun WANG, Hua-Tai LIN, Chia-Chu LIU
-
Patent number: 10282504Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.Type: GrantFiled: January 20, 2017Date of Patent: May 7, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yun-Lin Wu, Cheng-Cheng Kuo, Chia-Ping Chiang, Chih-Wei Hsu, Hua-Tai Lin, Kuei-Shun Chen, Yuan-Hsiang Lung, Yan-Tso Tsai
-
Patent number: 10274818Abstract: A photolithography system includes a substrate stage for holding a workpiece, and a mask having main patterns and sub-resolution assistant patterns. The system further includes a diffractive optical element (DOE) for directing a radiation having an aerial image of the main patterns onto the workpiece. The DOE includes a first pair of poles that is positioned symmetrically about a center of the DOE along a first direction. The main patterns are oriented lengthwise along a second direction that is perpendicular to the first direction. The sub-resolution assistant patterns are oriented lengthwise along the first direction.Type: GrantFiled: June 9, 2017Date of Patent: April 30, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hua-Tai Lin, Yu-Chuan Yang, Wen-Ta Liang, Ching-Huang Chen, Chi-Yuan Sun, Shih-Che Wang
-
Publication number: 20180174839Abstract: A photolithography system includes a substrate stage for holding a workpiece, and a mask having main patterns and sub-resolution assistant patterns. The system further includes a diffractive optical element (DOE) for directing a radiation having an aerial image of the main patterns onto the workpiece. The DOE includes a first pair of poles that is positioned symmetrically about a center of the DOE along a first direction. The main patterns are oriented lengthwise along a second direction that is perpendicular to the first direction. The sub-resolution assistant patterns are oriented lengthwise along the first direction.Type: ApplicationFiled: June 9, 2017Publication date: June 21, 2018Inventors: Hua-Tai Lin, Yu-Chuan Yang, Wen-Ta Liang, Ching-Huang Chen, Chi-Yuan Sun, Shih-Che Wang
-
Publication number: 20180137233Abstract: Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.Type: ApplicationFiled: January 11, 2018Publication date: May 17, 2018Inventors: Chin-Min Huang, Bo-Han Chen, Cherng-Shyan Tsay, Chien Wen Lai, Hua-Tai Lin, Chia-Cheng Chang, Lun-Wen Yeh, Shun-Shing Yang
-
Publication number: 20180096090Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.Type: ApplicationFiled: January 20, 2017Publication date: April 5, 2018Inventors: Yun-Lin Wu, Cheng-Cheng Kuo, Chia-Ping Chiang, Chih-Wei Hsu, Hua-Tai Lin, Kuei-Shun Chen, Yuan-Hsiang Lung, Yan-Tso Tsai