Patents by Inventor Hua-Tai Lin
Hua-Tai Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8848163Abstract: A lithography apparatus generates a tunable magnetic field to facilitate processing of photoresist. The lithography apparatus includes a chamber and a substrate stage in the chamber operable to hold a substrate. A magnetic module provides a magnetic field to the substrate on the substrate stage. The magnetic module is configured to provide the magnetic field in a tunable and alternating configuration with respect to its magnitude and frequency. The magnetic field is provided to have a gradient in magnitude along a Z-axis that is perpendicular to the substrate stage to cause magnetically-charged particles disposed over the substrate stage to move up and down along the Z-axis. The lithography apparatus also includes a radiation energy source and an objective lens configured to receive radiation energy from the radiation energy source and direct the radiation energy toward the substrate positioned on the substrate stage.Type: GrantFiled: March 17, 2011Date of Patent: September 30, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Cheng Wang, Chin-Hsiang Lin, Heng-Jen Lee, Ching-Yu Chang, Hua-Tai Lin, Burn Jeng Lin
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Publication number: 20140282334Abstract: The present disclosure provides a method of systematic defect extraction. Primary and secondary areas are defined in a wafer layout. A plurality of defects is identified by a first wafer inspection for an outside-process-window wafer. Defects located in the secondary area are removed. Defects associated with non-critical semiconductor features are also removed via a grouping process. Sensitive regions are defined around defects associated with critical semiconductor features. A second inspection is then performed on the sensitive regions for an inside-process-window wafer, thereby identifying a plurality of potentially systematic defects. Thereafter, a Scanning Electron Microscopy (SEM) process is performed to determine whether the defects in the sensitive regions of the inside-process-window wafer are true systematic defects.Type: ApplicationFiled: February 14, 2014Publication date: September 18, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jia-Rui Hu, Kai-Hsiung Chen, Chih-Mihg Ke, Hua-Tai Lin, Tsai-Sheng Gau
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Publication number: 20140256144Abstract: A mask set and method for forming FinFET semiconductor devices provides a complementary set of fin-cut masks that are used in DPT (double patterning technology) to remove fins from non-active areas of a semiconductor device, after the fins are formed. Adjacent fins, or adjacent groups of fins, are removed using pattern features from different ones of the multiple fin-cut masks.Type: ApplicationFiled: March 11, 2013Publication date: September 11, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tzu-Chun LO, Min-Hung CHENG, Hsiao-Wei SU, Jeng-Shiun HO, Ching-Che TSAI, Cheng-Cheng KUO, Hua-Tai LIN, Chia-Chu LIU, Kuei-Shun CHEN
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Publication number: 20140208283Abstract: Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The material layer has a closely spaced dense line structure, an isolated line structure next to the dense line structure, and a dummy line shoulder structure formed in the vicinity of the dense line and the isolated line structures. One end of the dummy line shoulder structure connects to the isolated line structure and another end extends away from the isolated line structure in an orientation substantially perpendicular to the isolated line structure.Type: ApplicationFiled: April 4, 2014Publication date: July 24, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Cheng Kuo, Tzu-Chun Lo, Ming-Hsing Tsai, Ken-Yu Chang, Jye-Yen Cheng, Jeng-Shiun Ho, Hua-Tai Lin, Chih-Hsiang Yao
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Patent number: 8765329Abstract: The present disclosure provides a photomask. The photomask includes a first integrated circuit (IC) feature formed on a substrate; and a second IC feature formed on the substrate and configured proximate to the first IC feature. The first and second IC features define a dense pattern having a first pattern density. The second IC feature is further extended from the dense pattern, forming an isolated pattern having a second pattern density less than the first pattern density. A transition region is defined from the dense pattern to the isolated pattern. The photomask further includes a sub-resolution rod (SRR) formed on the substrate, disposed in the transition region, and connected with the first IC feature.Type: GrantFiled: November 5, 2010Date of Patent: July 1, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jeng-Shiun Ho, Luke Lo, Ting-Chun Liu, Min-Hung Cheng, Jing-Wei Shih, Wen-Han Chu, Cheng-Cheng Kuo, Hua-Tai Lin, Tsai-Sheng Gau, Ru-Gun Liu, Yu-Hsiang Lin, Shang-Yu Huang
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Patent number: 8762900Abstract: A method of an integrated circuit (IC) design includes receiving an IC design layout. The IC design layout includes an IC feature with a first outer boundary and a first target points assigned to the first outer boundary. The method also includes generating a second outer boundary for the IC feature and moving all the first target points to the second outer boundary to form a modified IC design layout.Type: GrantFiled: June 27, 2012Date of Patent: June 24, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jaw-Jung Shin, Shy-Jay Lin, Hua-Tai Lin, Burn Jeng Lin
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Patent number: 8692351Abstract: Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The material layer has a closely spaced dense line structure, an isolated line structure next to the dense line structure, and a dummy line shoulder structure formed in the vicinity of the dense line and the isolated line structures. One end of the dummy line shoulder structure connects to the isolated line structure and another end extends away from the isolated line structure in an orientation substantially perpendicular to the isolated line structure.Type: GrantFiled: April 2, 2010Date of Patent: April 8, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng Cheng Kuo, Luke Lo, Minghsing Tsai, Ken-Yu Chang, Jye-Yen Cheng, Jeng-Shiun Ho, Hua-Tai Lin, Chih-Hsiang Yao
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Patent number: 8656319Abstract: A method of optical proximity correction (OPC) convergence control that includes providing a lithography system having a photomask and an illuminator. The method further includes performing an exposure by the illuminator on the photomask. Also, the method includes optimizing an optical illuminator setting for the lithography system with a defined gate pitch in a first direction in a first template. Additionally, the method includes determining OPC correctors to converge the OPC results with a target edge placement error (EPE) to produce a first OPC setting for the first template. The first OPC setting targets a relatively small EPE and mask error enhancement factor (MEEF)of the defined gate pitch in the first template. In addition, the method includes checking the first OPC setting for a relatively small EPE, MEEF and DOM consistency with the first template of the defined gate pitch in a second, adjacent template.Type: GrantFiled: February 8, 2012Date of Patent: February 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Cheng Kuo, Ching-Che Tsai, Tzu-Chun Lo, Chih-Wei Hsu, Hua-Tai Lin, Tsai-Sheng Gau, Wen-Chun Huang, Chih-Shiang Chou, Hsin-Chang Lee, Kuei Shun Chen
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Publication number: 20140035149Abstract: A semiconductor device includes a semiconductor substrate, a first active region in the semiconductor substrate, and a second active region in the semiconductor substrate. The semiconductor device further includes a first conductive line over the semiconductor substrate electrically connected to the first active region and having a first end face adjacent to the second active region, and the first end face having an image log slope of greater than 15 ?m-1.Type: ApplicationFiled: October 15, 2013Publication date: February 6, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jhun Hua CHEN, Yu-Lung TUNG, Chi-Tien CHEN, Hua-Tai LIN, Hsiang-Lin CHEN, Hung-Chang HSIEH, Yi-Fan CHEN
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Publication number: 20140007023Abstract: A method of an integrated circuit (IC) design includes receiving an IC design layout. The IC design layout includes an IC feature with a first outer boundary and a first target points assigned to the first outer boundary. The method also includes generating a second outer boundary for the IC feature and moving all the first target points to the second outer boundary to form a modified IC design layout.Type: ApplicationFiled: June 27, 2012Publication date: January 2, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jaw-Jung Shin, Shy-Jay Lin, Hua-Tai Lin, Burn Jeng Lin
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Patent number: 8589830Abstract: Provided is an integrated circuit (IC) design method. The method includes receiving an IC design layout having a feature with an outer boundary, performing a dissection on the feature to divide the outer boundary into a plurality of segments, and performing, using the segments, an optical proximity correction (OPC) on the feature to generate a modified outer boundary. The method also includes simulating a photolithography exposure of the feature with the modified outer boundary to create a contour and performing an OPC evaluation to determine if the contour is within a threshold. Additionally, the method includes repeating the performing a dissection, the performing an optical proximity correction, and the simulating if the contour does not meet the threshold, wherein each repeated dissection and each repeated optical proximity correction is performed on the modified outer boundary generated by the previously performed optical proximity correction.Type: GrantFiled: March 7, 2012Date of Patent: November 19, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Cheng Chang, Chin-Min Huang, Wei-Kuan Yu, Cherng-Shyan Tsay, Lai Chien Wen, Hua-Tai Lin
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Patent number: 8580637Abstract: A pattern on a semiconductor substrate is formed using two separate etching processes. The first etching process removes a portion of an intermediate layer above an active region of the substrate. The second etching process exposes a portion of the active region of the substrate. A semiconductor device formed using the patterning method has a decreased mask error enhancement factor and increased critical dimension uniformity than the prior art.Type: GrantFiled: December 16, 2011Date of Patent: November 12, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jhun Hua Chen, Yu-Lung Tung, Chi-Tien Chen, Hua-Tai Lin, Hsiang-Lin Chen, Hung Chang Hsieh, Yi-Fan Chen
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Publication number: 20130239071Abstract: Provided is an integrated circuit (IC) design method. The method includes receiving an IC design layout having a feature with an outer boundary, performing a dissection on the feature to divide the outer boundary into a plurality of segments, and performing, using the segments, an optical proximity correction (OPC) on the feature to generate a modified outer boundary. The method also includes simulating a photolithography exposure of the feature with the modified outer boundary to create a contour and performing an OPC evaluation to determine if the contour is within a threshold. Additionally, the method includes repeating the performing a dissection, the performing an optical proximity correction, and the simulating if the contour does not meet the threshold, wherein each repeated dissection and each repeated optical proximity correction is performed on the modified outer boundary generated by the previously performed optical proximity correction.Type: ApplicationFiled: March 7, 2012Publication date: September 12, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Cheng Chang, Chin-Min Huang, Wei-Kuan Yu, Cherng-Shyan Tsay, Lai Chien Wen, Hua-Tai Lin
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Patent number: 8507177Abstract: A material for use in lithography processing includes a polymer that turns soluble to a base solution in response to reaction with acid and a plurality of magnetically amplified generators (MAGs) each having a magnetic element and each decomposing to form acid bonded with the magnetic element in response to radiation energy.Type: GrantFiled: March 17, 2011Date of Patent: August 13, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Cheng Wang, Chin-Hsiang Lin, Heng-Jen Lee, Ching-Yu Chang, Hua-Tai Lin, Burn Jeng Lin
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Publication number: 20130205265Abstract: A method of optical proximity correction (OPC) convergence control that includes providing a lithography system having a photomask and an illuminator. The method further includes performing an exposure by the illuminator on the photomask. Also, the method includes optimizing an optical illuminator setting for the lithography system with a defined gate pitch in a first direction in a first template. Additionally, the method includes determining OPC correctors to converge the OPC results with a target edge placement error (EPE) to produce a first OPC setting for the first template. The first OPC setting targets a relatively small EPE and mask error enhancement factor (MEEF)of the defined gate pitch in the first template. In addition, the method includes checking the first OPC setting for a relatively small EPE, MEEF and DOM consistency with the first template of the defined gate pitch in a second, adjacent template.Type: ApplicationFiled: February 8, 2012Publication date: August 8, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Cheng Kuo, Ching-Che Tsai, Tzu-Chun Lo, Chih-Wei Hsu, Hua-Tai Lin, Tsai-Sheng Gau, Wen-Chun Huang, Chih-Shiang Chou, Hsin-Chang Lee, Kuei Shun Chen
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Publication number: 20130154100Abstract: A pattern on a semiconductor substrate is formed using two separate etching processes. The first etching process removes a portion of an intermediate layer above an active region of the substrate. The second etching process exposes a portion of the active region of the substrate. A semiconductor device formed using the patterning method has a decreased mask error enhancement factor and increased critical dimension uniformity than the prior art.Type: ApplicationFiled: December 16, 2011Publication date: June 20, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jhun Hua CHEN, Yu-Lung TUNG, Chi-Tien CHEN, Hua-Tai LIN, Hsiang-Lin CHEN, Hung-Chang HSIEH, Yi-Fan CHEN
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Publication number: 20120308112Abstract: In one embodiment, a method for extracting systematic defects is provided. The method includes inspecting a wafer outside a process window to obtain inspection data, defining a defect pattern from the inspection data, filtering defects from design data using a pattern search for the defined defect pattern within the design data, inspecting defects inside the process window with greater sensitivity than outside the process window, and determining systematic defects inside the process window. A computer readable storage medium, and a system for extracting systematic defects are also provided.Type: ApplicationFiled: June 2, 2011Publication date: December 6, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jia-Rui Hu, Te-Chih Huang, Chih-Ming Ke, Hua-Tai Lin, Tsai-Sheng Gau
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Publication number: 20120115073Abstract: The present disclosure provides a photomask. The photomask includes a first integrated circuit (IC) feature formed on a substrate; and a second IC feature formed on the substrate and configured proximate to the first IC feature. The first and second IC features define a dense pattern having a first pattern density. The second IC feature is further extended from the dense pattern, forming an isolated pattern having a second pattern density less than the first pattern density. A transition region is defined from the dense pattern to the isolated pattern. The photomask further includes a sub-resolution rod (SRR) formed on the substrate, disposed in the transition region, and connected with the first IC feature.Type: ApplicationFiled: November 5, 2010Publication date: May 10, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jeng-Shiun Ho, Luke Lo, Ting-Chun Liu, Min-Hung Cheng, Jing-Wei Shih, Wen-Han Chu, Cheng-Cheng Kuo, Hua-Tai Lin, Tsai-Sheng Gau, Ru-Gun Liu, Yu-Hsiang Lin, Shang-Yu Huang
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Patent number: 8101340Abstract: A method of inhibiting photoresist pattern collapse which includes the steps of providing a substrate; providing a photoresist layer on the substrate; exposing and developing the photoresist layer; applying a top anti-reflective coating layer to the photoresist layer; rinsing the photoresist layer; and drying the photoresist layer.Type: GrantFiled: May 9, 2007Date of Patent: January 24, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ching-Yu Chang, Heng-Jen Lee, Chin-Hsiang Lin, Hua-Tai Lin, Kuei Shun Chen, Bang-Chein Ho, Li-Kong Turn, Hung-Jui Kuo, Ko-Bin Kao, Tsung-Chih Chien
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Patent number: D676404Type: GrantFiled: April 25, 2012Date of Patent: February 19, 2013Inventor: Hua-Tai Lin