Abstract: Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The material layer has a closely spaced dense line structure, an isolated line structure next to the dense line structure, and a dummy line shoulder structure formed in the vicinity of the dense line and the isolated line structures. One end of the dummy line shoulder structure connects to the isolated line structure and another end extends away from the isolated line structure in an orientation substantially perpendicular to the isolated line structure.

Abstract: A material for use in lithography processing includes a polymer that turns soluble to a base solution in response to reaction with acid and a plurality of magnetically amplified generators (MAGs) each having a magnetic element and each decomposing to form acid bonded with the magnetic element in response to radiation energy.

Abstract: A material for use in lithography processing includes a polymer that turns soluble to a base solution in response to reaction with acid and a plurality of magnetically amplified generators (MAGs) each having a magnetic element and each decomposing to form acid bonded with the magnetic element in response to radiation energy.

Abstract: A material for use in lithography processing includes a polymer that turns soluble to a base solution in response to reaction with acid and a plurality of magnetically amplified generators (MAGs) each having a magnetic element and each decomposing to form acid bonded with the magnetic element in response to radiation energy.

Abstract: A photolithography system for printing a pattern of at least one contact or via on a wafer is provided. The system comprises a reticle having a layout, the layout comprises at least one polygon-shaped hole, wherein the at least one polygon-shaped hole comprises at least eight sides.

Abstract: A photomask including a main feature, corresponding to an integrated circuit feature, and a sub-resolution assist feature (SRAF) is provided. A first imaginary line tangential with a first edge of the main feature and a second imaginary line tangential with the second edge of the main feature define an area adjacent the main feature. A center point of the SRAF lies within this area. The SRAF may be a symmetrical feature. In an embodiment, the center point of the SRAF lies on an imaginary line extending at approximately 45-degree angle from a corner of a main feature.

Abstract: A photolithography system for printing a pattern of at least one contact or via on a wafer is provided. The system comprises a reticle having a layout, the layout comprises at least one polygon-shaped hole, wherein the at least one polygon-shaped hole comprises at least eight sides.

Abstract: An image reversal method is described that removes the etch resistance requirement from a resist. A high resolution resist pattern comprised of islands, lines, or trenches is formed with a large process window by exposing through one or more masks including phase edge masks and optionally with resolution enhancement techniques. A complementary material replacement (CMR) layer comprised of an organic polymer or material such as fluorosilicate glass which has a lower etch rate than the resist is coated over the resist pattern. CMR and resist layers are etched simultaneously to provide an image reversed pattern in the CMR layer which is etch transferred into a substrate. The method avoids edge roughness like bird's beak defects in the etched pattern and is useful for applications including forming contact holes in dielectric layers, forming polysilicon gates, and forming trenches in a damascene process. It is also valuable for direct write methods where an image reversal scheme is desired.

Abstract: A method for preserving semiconductor feature opening profiles for metrology examination including providing semiconductor wafer having a process surface comprising semiconductor feature openings; blanket depositing over the semiconductor feature openings to substantially fill the semiconductor feature openings at least one layer of material comprising silicon oxide; and, preparing a portion of the semiconductor wafer in cross sectional layout for metrology examination.

Abstract: A material for use in lithography processing includes a polymer that turns soluble to a base solution in response to reaction with acid and a plurality of magnetically amplified generators (MAGs) each having a magnetic element and each decomposing to form acid bonded with the magnetic element in response to radiation energy.

Abstract: A method of inhibiting photoresist pattern collapse which includes the steps of providing a substrate; providing a photoresist layer on the substrate; exposing and developing the photoresist layer; applying a top anti-reflective coating layer to the photoresist layer; rinsing the photoresist layer; and drying the photoresist layer.

Abstract: A method of fabricating semiconductor devices using dual damascene processes to form plugs in the via holes composed of various high etch materials and bottom anti-reflection coating (BARC) materials. After via hole etch, a layer of high etch rate plug material is spin coated to fill the via holes. Next, a layer of photoresist is applied. The photoresist is then exposed through a mask and developed to form an etch opening. Using the remaining photoresist as an etch mask and with a bottom anti-reflection coating (BARC) as protection, the oxide or low k layer is etched to form subsequent wiring. The etch step is known as a damascene etch step. The remaining photoresist is removed and the trench/via openings are filled with metal forming inlaid metal interconnect wiring and contact vias.

Abstract: A method of manufacturing a microlens includes forming a photoresist layer over a substrate having a photo sensor located therein and exposing the photoresist layer in an exposure system having a lower resolution. The exposure uses a photomask having a microlens pattern comprising a plurality of dark regions and clear regions alternately disposed. The photoresist is developed to from the microlens having a curved shape.

Abstract: Provided are a system and method for modifying a fabrication process based on inline measurement information during manufacture of a semiconductor device. In one example, the method includes exposing a photoresist layer on the device, performing post-exposure baking on the photoresist layer, and obtaining at least one critical dimension (CD) measurement of the device. A determination may be made as to whether the CD measurement indicates that the exposure and/or baking step achieved a predefined result. If not, the device may be subjected to additional exposure or baking.

Abstract: Disclosed is a photomask comprising a transparent substrate, an absorption layer proximate to the transparent substrate, and a pellicle mounted proximate to the transparent substrate. The absorption layer has at least one opening formed therein for receiving a wavelength-reducing material (WRM). The wavelength-reducing material and the absorption layer form a generally planar surface.

Abstract: A novel method and apparatus for reducing or eliminating electrostatic charging of wafers during a spin-dry step of wafer cleaning is disclosed. The method includes rinsing a wafer, typically by dispensing a cleaning liquid such as deionized water on the wafer while spinning the wafer; and spin-drying the wafer by sequentially rotating the wafer in opposite directions. The apparatus includes a wafer support platform that is capable of sequentially rotating a wafer in opposite directions to spin-dry the wafer.

Abstract: A new and improved method for measuring dimensions of a photoresist pattern profile on a wafer substrate during photolithography for the fabrication of integrated circuits on the substrate. According to one embodiment, the method includes fixing the photoresist pattern profile on the substrate using a spin-on glass (SOG) procedure. In another embodiment, the method includes fixing the photoresist pattern profile on the substrate using a sputter oxide (SO) procedure. The fixed photoresist pattern is then subjected to a microscopy procedure, typically transmission electron microscopy (TEM), to measure the exact linewidth and other dimensions of the profile. The method prevents distortion of the profile during fixation and facilitates an accurate determination of the profile dimensions.

Abstract: A method of fabricating semiconductor devices using dual damascene processes to form plugs in the via holes composed of various high etch materials and bottom anti-reflection coating (BARC) materials. After via hole etch, a layer of high etch rate plug material is spin coated to fill the via holes. Next, a layer of photoresist is applied. The photoresist is then exposed through a mask and developed to form an etch opening. Using the remaining photoresist as an etch mask and with a bottom anti-reflection coating (BARC) as protection, the oxide or low k layer is etched to form subsequent wiring. The etch step is known as a damascene etch step. The remaining photoresist is removed and the trench/via openings are filled with metal forming inlaid metal interconnect wiring and contact vias.

Abstract: A new and improved method for measuring dimensions of a photoresist pattern profile on a wafer substrate during photolithography for the fabrication of integrated circuits on the substrate. According to one embodiment, the method includes fixing the photoresist pattern profile on the substrate using a spin-on glass (SOG) procedure. In another embodiment, the method includes fixing the photoresist pattern profile on the substrate using a sputter oxide (SO) procedure. The fixed photoresist pattern is then subjected to a microscopy procedure, typically transmission electron microscopy (TEM), to measure the exact linewidth and other dimensions of the profile. The method prevents distortion of the profile during fixation and facilitates an accurate determination of the profile dimensions.

Abstract: A method for preserving semiconductor feature opening profiles for metrology examination including providing semiconductor wafer having a process surface comprising semiconductor feature openings; blanket depositing over the semiconductor feature openings to substantially fill the semiconductor feature openings at least one layer of material comprising silicon oxide; and, preparing a portion of the semiconductor wafer in cross sectional layout for metrology examination.