Patents by Inventor Hua Wei
Hua Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978417Abstract: A pixel array substrate includes multiple data lines, multiple scan lines and multiple pixel structures. The scan lines include an m-th scan line and an (m+1)-th scan line arranged in sequence, and m is a positive integer. The pixel structures include first to twenty-fourth pixel structures. A control terminal of a transistor of the seventh pixel structure and a control terminal of a transistor of the eighth pixel structure are electrically connected to the (m+1)-th scan line and the m-th scan line respectively. A control terminal of a transistor of the thirteenth pixel structure and a control terminal of a transistor of the fourteenth pixel structure are electrically connected to the (m+1)-th scan line and the m-th scan line respectively.Type: GrantFiled: June 26, 2023Date of Patent: May 7, 2024Assignee: AUO CorporationInventors: Shiuan-Hua Huang, Lin-Chieh Wei, Chun-Min Wang
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Publication number: 20240134180Abstract: An optical device and the prism module thereof are provided. The prism module includes a first prism, a second prism, and a third prism. The second prism is disposed beside the first prism. The third prism is adhered to the second prism. First light enters the first prism, is reflected plural times in the first prism, enters the second prism, and is emitted from the second prism. Second light enters the second prism, is reflected plural times in the second prism, and is emitted from the second prism. Third light sequentially passes through the third prism and the second prism, enters the first prism, is reflected plural times in the first prism, and is emitted from the first prism.Type: ApplicationFiled: October 19, 2023Publication date: April 25, 2024Inventors: Fei Han, Xiao-Yao Zhang, Yue-Ye Chen, Ling-Wei Zhao, Jun-Wei Che, Hua-Tang Liu
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Publication number: 20240132473Abstract: The present invention relates to the technical field of biomedicine, in particular to a sulfoximide substituted indazole compound, an isomer thereof, or a pharmaceutically acceptable salt thereof.Type: ApplicationFiled: December 19, 2023Publication date: April 25, 2024Applicant: Shanghai Xunhe Pharmaceutical Technology Co. Ltd.Inventors: Nongnong WEI, Hua JIN, Yongyong ZHENG, Feng ZHOU, Meihua HUANG
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Patent number: 11967546Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.Type: GrantFiled: July 21, 2022Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang, Chih-Ta Shen, Szu-Wei Lu, Ying-Ching Shih, Wen-Chih Chiou, Chi-Hsi Wu, Chen-Hua Yu
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Publication number: 20240126361Abstract: A handheld controller is adapted to control an electronic device. The handheld controller includes a first body, a second body, and a connecting portion. The first body is adapted to be held by a user's hand. The second body is connected to the first body through the connecting portion. The connecting portion is adapted to be clamped between user's fingers. A distance between the first body and at least a portion of the second body is variable.Type: ApplicationFiled: February 24, 2023Publication date: April 18, 2024Applicant: HTC CorporationInventors: Chang-Hua Wei, Yu-Ling Huang
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Publication number: 20240128211Abstract: Some implementations described herein provide techniques and apparatuses for a stacked semiconductor die package. The stacked semiconductor die package may include an upper semiconductor die package above a lower semiconductor die package. The stacked semiconductor die package includes one or more rows of pad structures located within a footprint of a semiconductor die of the lower semiconductor die package. The one or more rows of pad structures may be used to mount the upper semiconductor die package above the lower semiconductor die package. Relative to another stacked semiconductor die package including a row of dummy connection structures adjacent to the semiconductor die that may be used to mount the upper semiconductor die package, a size of the stacked semiconductor die package may be reduced.Type: ApplicationFiled: April 27, 2023Publication date: April 18, 2024Inventors: Chih-Wei WU, An-Jhih SU, Hua-Wei TSENG, Ying-Ching SHIH, Wen-Chih CHIOU, Chun-Wei CHEN, Ming Shih YEH, Wei-Cheng WU, Der-Chyang YEH
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Publication number: 20240124241Abstract: A transporting device can transport at least one product, the transporting device includes a mounting frame, a driving mechanism, a transmitting mechanism including a plurality of bent portions, a plurality of guiding mechanisms, and a supporting mechanism. Each guiding mechanism includes a rotating wheel and a guiding plate. Each bent portion is connected to the rotating wheel. The guiding plate is connected to the rotating wheel. The supporting mechanism can support the product. The driving mechanism is further connected to the rotating wheel and can drive the transmitting mechanism to rotate to drive the supporting mechanism to move. The driving mechanism is further connected to the guiding plate, the guiding plate and the rotating wheel can synchronously rotate to drive the supporting mechanism to pass through the bent portions. The present disclosure further provides a heating device.Type: ApplicationFiled: December 27, 2023Publication date: April 18, 2024Inventors: Huan ZHANG, Qi KUANG, Hua WAN, Yi LIU, Wei-Wei WU, Jing-Chao YANG, Wen-Jin XIA
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Publication number: 20240128143Abstract: Provided are a package structure and a method of forming the same. The method includes: forming an interconnect structure on a substrate; performing a laser grooving process to form a first opening in the interconnect structure and form a debris layer on a sidewall of the first opening in a same step; forming a protective layer to fill in the first opening and cover the debris layer and the interconnect structure; patterning the protective layer to form a second opening, wherein the second opening is spaced from the debris layer by the protective layer; performing a planarization process on the protective layer to expose a topmost contact pad of the interconnect structure; and performing a mechanical dicing process through the second opening to form a third opening in the substrate and cut the substrate into a plurality of semiconductor dies.Type: ApplicationFiled: February 1, 2023Publication date: April 18, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Han Hsieh, Yu-Jin Hu, Hua-Wei Tseng, An-Jhih Su, Der-Chyang Yeh
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Patent number: 11961796Abstract: A package comprises at least one first device die, and a redistribution line (RDL) structure having the at least one first device die bonded thereto. The RDL structure comprises a plurality of dielectric layers, and a plurality of RDLs formed through the plurality of dielectric layers. A trench is defined proximate to axial edges of the RDL structure through each of the plurality of dielectric layers. The trench prevents damage to portions of the RDL structure located axially inwards of the trench.Type: GrantFiled: August 30, 2021Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yueh-Ting Lin, Hua-Wei Tseng, Ming Shih Yeh, Der-Chyang Yeh
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Patent number: 11961738Abstract: In a method of forming a pattern, a first pattern is formed over an underlying layer, the first pattern including main patterns and a lateral protrusion having a thickness of less than 25% of a thickness of the main patterns, a hard mask layer is formed over the first pattern, a planarization operation is performed to expose the first pattern without exposing the lateral protrusion, a hard mask pattern is formed by removing the first pattern while the lateral protrusion being covered by the hard mask layer, and the underlying layer is patterned using the hard mask pattern as an etching mask.Type: GrantFiled: February 12, 2021Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Ta Chen, Hua-Tai Lin, Han-Wei Wu, Jiann-Yuan Huang
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Publication number: 20240115713Abstract: Disclosed are a polyethylene glycol conjugate drug, and a preparation method therefor and the use thereof. Specifically, the present invention relates to a polyethylene glycol conjugate drug represented by formula A or a pharmaceutically acceptable salt thereof, a method for preparing the polyethylene glycol conjugate drug or the pharmaceutically acceptable salt thereof, an intermediate for preparing the polyethylene glycol conjugate drug or the pharmaceutically acceptable salt thereof, a pharmaceutical composition comprising the polyethylene glycol conjugate drug or the pharmaceutically acceptable salt thereof, and the use of the polyethylene glycol conjugate drug or the pharmaceutically acceptable salt thereof in the preparation of a drug.Type: ApplicationFiled: July 21, 2021Publication date: April 11, 2024Inventors: Gaoquan LI, Nian LIU, Yongchen PENG, Xiafan ZENG, Gang MEI, Sheng GUAN, Yang GAO, Shuai YANG, Yifeng YIN, Jie LOU, Huiyu CHEN, Kun QIAN, Yusong WEI, Qian ZHANG, Dajun LI, Xiaoling DING, Xiangwei YANG, Liqun HUANG, Xi LIU, Liwei LIU, Zhenwei LI, Kaixiong HU, Hua LIU, Tao TU
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Patent number: 11951540Abstract: Provided is a supergravity directional solidification melting furnace equipment, including a supergravity test chamber and, mounted in the supergravity test chamber, a high-temperature heating subsystem, a crucible, and an air-cooling system. The supergravity test chamber is mounted with a wiring electrode and a cooling air valve device. The high-temperature heating subsystem is fixed in the supergravity test chamber. The crucible and the air cooling system are provided in the high-temperature heating subsystem. The high-temperature heating subsystem includes upper, middle, and lower furnaces, a mullite insulating layer, upper and lower heating cavity outer bodies, upper and lower heating furnace pipes, and a crucible support base. A high-temperature heating cavity is divided into upper and lower parts, is provided therein with a spiral groove, and is fitted with a heating element. The crucible support base is provided therein with a vent pipe channel into which a cooling air is introduced.Type: GrantFiled: February 27, 2020Date of Patent: April 9, 2024Assignee: ZHEJIANG UNIVERSITYInventors: Hua Wei, Yadan Xie, Jianjiang Zhao, Weian Lin, Ze Zhang, Yunmin Chen
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Patent number: 11951382Abstract: Various powered personal mobility vehicles are disclosed. In some embodiments, the vehicle can include a deck having a forward portion, a rearward portion, and a neck portion. A front swivel wheel assembly and a rear swivel wheel assembly can be connected with the deck. In some embodiments, the front swivel wheel assembly comprises a motor.Type: GrantFiled: March 5, 2020Date of Patent: April 9, 2024Inventors: Robert (Wei-Pin) Chen, Hua Tao, Huolai Guo
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Patent number: 11954986Abstract: A self-service apparatus having a three-layer system architecture includes an application-layer device, an intermediate-layer device, and bottom-layer peripheral devices. The application-layer device is configured to provide a user interface for self-service and control the entire self-service apparatus according to an interaction with the user to provide the user with required self-service, and comprises a first processor and a first memory. The first processor executes an application program stored in the first memory and communicates with the intermediate-layer device. The intermediate-layer device comprises a terminal control module which comprises a second processor and a second memory. The second processor communicates with the bottom-layer peripheral devices, and the second processor executes a control program stored in the second memory to control operations of the peripheral devices based on an instruction from the application-layer device.Type: GrantFiled: April 22, 2020Date of Patent: April 9, 2024Assignee: Elo Touch Solutions, Inc.Inventors: Yin Sun, Xueqing Wei, Jinfeng Zhang, Hua Shao
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Publication number: 20240105518Abstract: A first group of semiconductor fins are over a first region of a substrate, the substrate includes a first stepped profile between two of the first group of semiconductor fins, and the first stepped profile comprises a first lower step, two first upper steps, and two first step rises extending from opposite sides of the first lower step to the first upper steps. A second group of semiconductor fins are over a second region of the substrate, the substrate includes a second stepped profile between two of the second group of semiconductor fins, and the second stepped profile comprises a second lower step, two second upper steps, and two second step rises extending from opposite sides of the second lower step to the second upper steps, in which the second upper steps are wider than the first upper steps in the cross-sectional view.Type: ApplicationFiled: January 11, 2023Publication date: March 28, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Ta CHEN, Han-Wei WU, Yuan-Hsiang LUNG, Hua-Tai LIN
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Publication number: 20240068917Abstract: An integrated acoustic detection and rock direct tensile test machine includes a support frame. A top of the support frame is provided with a top plate and a bearing plate is provided above the top plate. The bearing plate is provided with force transferring rods, lower ends of which are provided with a tensile base. A top of the tensile base is provided with a lower clamp holder and a bottom of the top plate is provided with an upper clamp holder. An upper channel is provided inside the upper clamp holder. The upper channel is provided with an acoustic transmitting probe. A lower channel is provided inside the lower clamp holder. One end of the lower channel is communicated with the outside, the other end is provided with an acoustic receiving probe. The lower channel extends to a bottom of a clamping chamber of the lower clamp holder.Type: ApplicationFiled: August 24, 2023Publication date: February 29, 2024Inventors: Huining XU, Tianqi LIU, Jianfeng LIU, Fujun XUE, Jingjing DAI, Lu WANG, Lina RAN, Yougang CAI, Jianliang PEI, Hua LI, Jinbing WEI, Jianhui DENG
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Publication number: 20240063637Abstract: The present disclosure discloses a grid supply load predicting method, a system, and a storage medium. The method includes: determining a characteristic historical data set of a grid supply load; obtaining a grid supply load characteristic trend prediction result by inputting the characteristic data set of the historical grid supply load and the daily characteristic data of target influencing factor into a preset trend prediction model for grid supply load characteristic trend prediction; determining a grid supply load curve type; obtaining a grid supply load prediction model corresponding to the grid supply load curve type to take as a target prediction model; and obtaining a target grid supply load prediction result by inputting the historical data set of the grid supply load, the grid supply load characteristic trend prediction result and the daily characteristic data of target influencing factor into the target prediction model for grid supply load prediction.Type: ApplicationFiled: August 18, 2022Publication date: February 22, 2024Inventors: Biyun CHEN, Qi XU, Bin LI, Xiaoqing BAI, Yun ZHU, Peijie LI, Chi ZHANG, Yude YANG, Hua WEI
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Patent number: 11907711Abstract: Aspects of the invention include systems and methods configured to efficiently evaluate the efforts of a code migration (e.g., porting task) between different platforms. A non-limiting example computer-implemented method includes receiving a function of a source platform. The function can include a plurality of fields. An initial vector is constructed for each of the plurality of fields. The initial vector encodes a value of the respective field according to an encoding rule. The initial vectors are merged into a single final vector and the final vector is classified into one of a plurality of system function families of the source platform. A vector of a target platform at a minimum distance to the final vector is identified and an assessment is provided that includes a difficulty in porting a project comprising the function between the source platform and the target platform based at least in part on the minimum distance.Type: GrantFiled: May 13, 2021Date of Patent: February 20, 2024Assignee: International Business Machines CorporationInventors: Shuang Shuang Jia, Yi Chai, Xiao-Yu Li, Xin Zhao, Li Cao, Jiangang Deng, Hua Wei Fan, Zhou Wen Ya, Hong Wei Sun
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Publication number: 20240055311Abstract: A semiconductor structure includes a package, an electrical device and an underfill material. The package includes a redistribution structure and at least one die, and the at least one die is disposed on a first side of the redistribution structure. The electrical device is disposed on a second side of the redistribution structure, the electrical device has a top surface and a bottom surface opposite to each other, and the top surface faces the redistribution structure. The underfill material is disposed between the top surface and the redistribution structure and extending toward the bottom surface, the underfill material has an end surface corresponding to the bottom surface, and the end surface is a flat surface. In addition, a manufacturing method of the semiconductor structure is also provided.Type: ApplicationFiled: August 14, 2022Publication date: February 15, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yueh-Ting Lin, Hua-Wei Tseng, An-Jhih Su, Ming-Shih Yeh, Der-Chyang Yeh
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Publication number: 20240030168Abstract: A package structure is provided. The package structure includes a bottom die and a top die. The bottom die includes: a first active region surrounded by a first seal ring region; a first seal ring region including a bottom seal ring; and a first bonding layer disposed on a front side of the bottom die. The top die includes: a second active region surrounded by a second seal ring region; a second seal ring region including a top seal ring; and a second bonding layer disposed on a front side of the top die. The bottom die and the top die are bonded through hybrid bonding between the first bonding layer and the second bonding layer at an interface therebetween such that the bottom seal ring and the top seal ring are vertically aligned and are operable to form a continuous seal ring.Type: ApplicationFiled: July 24, 2022Publication date: January 25, 2024Inventors: Wei-Yu Chen, Hua-Wei Tseng, Li-Hsien Huang, Yinlung Lu, Jun He