Patents by Inventor Hua Wei

Hua Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11844288
    Abstract: An in-plane magnetized spin-orbit magnetic device is provided. The in-plane magnetized spin-orbit magnetic device includes a heavy metal layer, an upper electrode and a magnetic tunnel junction. The magnetic tunnel junction is disposed between the heavy metal layer and the upper electrode. The magnetic tunnel junction includes a free layer and a pinned layer. The free layer is disposed on the heavy metal layer, and the free layer has a first film plane area. The pinned layer is disposed on the free layer, and the pinned layer has a second film plane area. There is a preset angle between a long axis direction of a film plane shape of the free layer and a long axis direction of a film plane shape of the pinned layer, and the first film plane area is larger than the second film plane area.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: December 12, 2023
    Assignee: Industrial Technology Research Institute
    Inventors: Hsin-Han Lee, Jeng-Hua Wei, I-Jung Wang, Shan-Yi Yang, Yao-Jen Chang
  • Publication number: 20230386989
    Abstract: A package comprises at least one first device die, and a redistribution line (RDL) structure having the at least one first device die bonded thereto. The RDL structure comprises a plurality of dielectric layers, and a plurality of RDLs formed through the plurality of dielectric layers. A trench is defined proximate to axial edges of the RDL structure through each of the plurality of dielectric layers. The trench prevents damage to portions of the RDL structure located axially inwards of the trench.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yueh-Ting Lin, Hua-Wei Tseng, Ming Shih Yeh, Der-Chyang Yeh
  • Publication number: 20230363086
    Abstract: An electronic device includes a circuit board, a shielding member, and a testing pin. The circuit board includes a grounding area. The shielding member is located on a side of the circuit board and includes a shielding layer and an insulating layer. The shielding layer is electrically connected to the grounding area. The insulating layer is located on a side of the shielding layer away from the circuit board. The testing pin is disposed on the circuit board and electrically connected to the shielding layer.
    Type: Application
    Filed: May 6, 2022
    Publication date: November 9, 2023
    Inventors: Li Hua Wei, Ming Hsiang Lin, Shih Hao Chen, Cai Jin Ye
  • Publication number: 20230307005
    Abstract: A method and a system for audiovisual signal synchronization are provided. The method is adapted to an audiovisual system. When the audiovisual system is in operation, a circuit for distributed audiovisual synchronization-calibration is provided for acquiring delay information reported by various audiovisual circuit modules that are in charge of processing audiovisual signals. Accordingly, the audiovisual synchronization processing system that is disposed in the audiovisual system to synchronize the audiovisual signals can obtain a time difference between audio signals and video signals. When processing audio and video data, the audiovisual system can utilize the time difference to synchronize the audio signals and the video signals, and then output an audiovisual content.
    Type: Application
    Filed: March 20, 2023
    Publication date: September 28, 2023
    Inventors: SHIH-HUA WEI, YUNG-JUI LEE, TING-PANG TSAO
  • Patent number: 11758821
    Abstract: A magnetic memory structure includes a heavy-metal layer, a plurality of magnetic tunneling junction (MTJ) layer, a conductive layer and an insulation layer. In an example, the pinned-layer of the MTJ layers are arranged in a string form and disposed over the barrier-layer. In an example also disclosed, the pinned-layer, the free-layer of the MTJ layers are arranged in a string form. Whereas the pinned-layers are disposed over the barrier-layer and the free-layers are disposed over the heavy-metal layer. The conductive layer is formed under the heavy-metal layer and includes a first conductive portion and a second conductive portion separated from each other and connected with two end of the heavy-metal layer respectively. The insulation layer fills up an interval between the first conductive portion and the second conductive portion. The conductive layer has an electric conductivity higher than that of the heavy-metal layer.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: September 12, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ziaur Rahaman Shakh, I-Jung Wang, Jeng-Hua Wei
  • Publication number: 20230275040
    Abstract: A method includes forming a reconstructed wafer including encapsulating a device die in an encapsulant, forming a dielectric layer over the device die and the encapsulant, forming a plurality of redistribution lines extending into the dielectric layer to electrically couple to the device die, and forming a metal ring in a common process for forming the plurality of redistribution lines. The metal ring encircles the plurality of redistribution lines, and the metal ring extends into scribe lines of the reconstructed wafer. A die-saw process is performed along scribe lines of the reconstructed wafer to separate a package from the reconstructed wafer. The package includes the device die and at least a portion of the metal ring.
    Type: Application
    Filed: May 5, 2023
    Publication date: August 31, 2023
    Inventors: Wan-Yu Lee, Chiang Lin, Yueh-Ting Lin, Hua-Wei Tseng, Li-Hsien Huang, Yu-Hsiang Hu
  • Publication number: 20230229581
    Abstract: Examples described herein provide a computer-implemented method for identifying regression test failures that includes comparing a base code to a new code to locate an updated aspect of a program. The method further includes inserting debug code into corresponding source files for each of the base code and the new code for the updated aspect. The method further includes building a first image for the base code and a second image for the new code, the first and second images running in respective first and second containers. The method further includes comparing debugging outputs from a regression test of the respective first and second containers to identify a regression test failure. The method further includes implementing a corrective action to correct the regression test failure.
    Type: Application
    Filed: January 18, 2022
    Publication date: July 20, 2023
    Inventors: Xiao-Yu Li, Hua Wei Fan, Jiangang Deng, Hong Wei Sun, Xiao Ling Chen, Wen Ji Huang
  • Patent number: 11693046
    Abstract: A test and measurement instrument including a signal generator configured to generate a waveform to be sent over a cable to a device under test (DUT) and a real-time waveform monitor (RTWM) circuit. The RTWM is configured to determine a propagation delay of the cable, capture a first waveform, including an incident waveform and a reflection waveform at a first test point between the signal generator and the DUT, capture a second waveform including at least the incident waveform at a second test point between the signal generator and the DUT, determine a reflection waveform and the incident waveform based on the first waveform and the second waveform, and determine a DUT waveform based on the incident waveform, the reflection waveform, and the propagation delay. The DUT waveform represents the waveform generated by the signal generator as received by the DUT.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: July 4, 2023
    Assignee: Tektronix, Inc.
    Inventors: Yufang Li, Sicong Zhu, Hua Wei, Fan Huang, Ye Yang
  • Patent number: 11682637
    Abstract: A method includes forming a reconstructed wafer including encapsulating a device die in an encapsulant, forming a dielectric layer over the device die and the encapsulant, forming a plurality of redistribution lines extending into the dielectric layer to electrically couple to the device die, and forming a metal ring in a common process for forming the plurality of redistribution lines. The metal ring encircles the plurality of redistribution lines, and the metal ring extends into scribe lines of the reconstructed wafer. A die-saw process is performed along scribe lines of the reconstructed wafer to separate a package from the reconstructed wafer. The package includes the device die and at least a portion of the metal ring.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: June 20, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Yu Lee, Chiang Lin, Yueh-Ting Lin, Hua-Wei Tseng, Li-Hsien Huang, Yu-Hsiang Hu
  • Publication number: 20230178130
    Abstract: An in-plane magnetized spin-orbit magnetic device is provided. The in-plane magnetized spin-orbit magnetic device includes a heavy metal layer, an antiferromagnetic layer, and a magnetic tunnel junction. The antiferromagnetic layer is disposed on the heavy metal layer, and the magnetic tunnel junction is disposed on the antiferromagnetic layer. The magnetic tunnel junction includes a free layer, a barrier layer, and a pinned layer. The barrier layer is disposed on the free layer, and the pinned layer is disposed on the barrier layer. A film surface shape of the free layer is a rounded rectangle.
    Type: Application
    Filed: December 28, 2021
    Publication date: June 8, 2023
    Applicant: Industrial Technology Research Institute
    Inventors: Hsin-Han Lee, Jeng-Hua Wei, I-Jung Wang, Shan-Yi Yang, Yao-Jen Chang, Fang-Ming Chen
  • Publication number: 20230170258
    Abstract: An integrated circuit chip package and a method of fabricating the same are disclosed. The method includes forming a device layer on a substrate with a first die and a second die, forming an interconnect structure on the device layer, depositing an insulating layer on the interconnect structure, forming first and second conductive pads on the interconnect structure, forming first and second conductive vias on the first and second conductive pads, respectively, patterning a polymer layer to form first and second buffer layers with tapered side profiles on the first and second conductive vias, respectively, forming a trench in the substrate and between the first and second buffer layers, and dicing the substrate through the trench to separate the first die from the second die. Portions of the first and second conductive pads extend over the insulating layer.
    Type: Application
    Filed: June 6, 2022
    Publication date: June 1, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Hsien HUANG, Yao-Chun CHUANG, Hua-Wei TSENG, Yu-Jin HU, Jun HE
  • Publication number: 20230154881
    Abstract: A package structure including IPD and method of forming the same are provided. The package structure includes a die, an encapsulant laterally encapsulating the die, a first RDL structure disposed on the encapsulant and the die, an IPD disposed on the first RDL structure and an underfill layer. The IPD includes a substrate, a first connector on a first side of the substrate and electrically connected to the first RDL structure, a guard structure on a second side of the substrate opposite to the first side and laterally surrounding a connector region, and a second connector disposed within the connector region and electrically connected to a conductive via embedded in the substrate. The underfill layer is disposed to at least fill a space between the first side of the IPD and the first RDL structure. The underfill layer is separated from the connector region by the guard structure.
    Type: Application
    Filed: January 17, 2023
    Publication date: May 18, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hua-Wei Tseng, Yueh-Ting Lin, Shao-Yun Chen, Li-Hsien Huang, An-Jhih Su, Ming-Shih Yeh, Der-Chyang Yeh
  • Patent number: 11625588
    Abstract: A neuron circuit and an artificial neural network chip are provided. The neuron circuit includes a memristor and an integrator. The memristor generates a pulse train having an oscillation frequency when an applied voltage exceeds a predetermined threshold. The integrator is connected in parallel to the memristor for receiving and accumulating input pulses transmitted by a previous layer network at different times, and driving the memristor to transmit the pulse train to a next layer network when a voltage of the accumulated input pulses exceeds the predetermined threshold.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: April 11, 2023
    Assignee: Industrial Technology Research Institute
    Inventors: Tuo-Hung Hou, Shyh-Shyuan Sheu, Jeng-Hua Wei, Heng-Yuan Lee, Ming-Hung Wu
  • Patent number: 11609165
    Abstract: Provided is a material performance testing system under a fixed multi-field coupling effect in a hypergravity environment, including a hoisted sealed cabin, a bearing frame, a high-temperature furnace, a mechanical test device, and a buffer device. The bearing frame and the high-temperature furnace are fixedly mounted inside the hoisted sealed cabin. The bearing frame is covered on the high-temperature furnace. The buffer device is mounted at a bottom of the high-temperature furnace. Upper and lower ends of the mechanical test device are connected in a top of the bearing frame and the bottom of the high-temperature furnace. A sample is connected and mounted at an end of the mechanical test device.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: March 21, 2023
    Assignee: ZHEJIANG UNIVERSITY
    Inventors: Hua Wei, Jiangwei Wang, Weian Lin, Ze Zhang, Yunmin Chen
  • Publication number: 20230068082
    Abstract: A package comprises at least one first device die, and a redistribution line (RDL) structure having the at least one first device die bonded thereto. The RDL structure comprises a plurality of dielectric layers, and a plurality of RDLs formed through the plurality of dielectric layers. A trench is defined proximate to axial edges of the RDL structure through each of the plurality of dielectric layers. The trench prevents damage to portions of the RDL structure located axially inwards of the trench.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yueh-Ting Lin, Hua-Wei Tseng, Ming Shih Yeh, Der-Chyang Yeh
  • Patent number: 11587900
    Abstract: A package structure including IPD and method of forming the same are provided. The package structure includes a die, an encapsulant laterally encapsulating the die, a first RDL structure disposed on the encapsulant and the die, an IPD disposed on the first RDL structure and an underfill layer. The IPD includes a substrate, a first connector on a first side of the substrate and electrically connected to the first RDL structure, a guard structure on a second side of the substrate opposite to the first side and laterally surrounding a connector region, and a second connector disposed within the connector region and electrically connected to a conductive via embedded in the substrate. The underfill layer is disposed to at least fill a space between the first side of the IPD and the first RDL structure. The underfill layer is separated from the connector region by the guard structure.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: February 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hua-Wei Tseng, Yueh-Ting Lin, Shao-Yun Chen, Li-Hsien Huang, An-Jhih Su, Ming-Shih Yeh, Der-Chyang Yeh
  • Patent number: D978145
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: February 14, 2023
    Assignee: HTC Corporation
    Inventors: Chang-Hua Wei, Pei-Pin Huang
  • Patent number: D997225
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: August 29, 2023
    Assignee: HTC Corporation
    Inventors: Chang-Hua Wei, Chung-Wei Li
  • Patent number: D1000622
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: October 3, 2023
    Assignee: Alura Inc.
    Inventors: Shi Ze Hua, Hua Wei, Liu Guo
  • Patent number: D1011426
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: January 16, 2024
    Assignee: HTC Corporation
    Inventors: Pei-Pin Huang, Chang-Hua Wei, Chung-Wei Li, Yu-Lin Huang